Team, Visitors, External Collaborators
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
XML PDF e-pub
PDF e-Pub


Bibliography

Major publications by the team in recent years
[1]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[2]
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
High-Level Synthesis of Loops Using the Polyhedral Model - 12, in: High-Level Synthesis From Algorithm to Digital Circuit, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.
https://doi.org/10.1007/978-1-4020-8588-8_12
[3]
C. Huriaux, A. Courtay, O. Sentieys.
Design Flow and Run-Time Management for Compressed FPGA Configurations, in: IEEE/ACM Design, Automation and Test in Europe (DATE), March 2015.
https://hal.inria.fr/hal-01089319
[4]
J.-M. Jézéquel, B. Combemale, S. Derrien, C. Guy, S. Rajopadhye.
Bridging the Chasm Between MDE and the World of Compilation, in: Journal of Software and Systems Modeling (SoSyM), October 2012, vol. 11, no 4, pp. 581-597. [ DOI : 10.1007/s10270-012-0266-8 ]
https://hal.inria.fr/hal-00717219
[5]
B. Le Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on VLSI Systems, 2008, vol. 16, no 11, pp. 1454-1464.
[6]
K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation, in: ACM transactions on Reconfigurable Technology and Systems (TRETS), June 2012, vol. 5, no 2, pp. 1-38.
http://doi.acm.org/10.1145/2209285.2209289
[7]
D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: Proc. ACM/IEEE CASES, October 2002.
[8]
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[9]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13.
[10]
R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations, in: IEEE Transactions on Circuits and Systems. Part I, Regular Papers, October 2012, vol. 59, no 10, pp. 2326 - 2339. [ DOI : 10.1109/TCSI.2012.2188938 ]
http://hal.inria.fr/hal-00741741
[11]
C. Wolinski, M. Gokhale, K. McCabe.
A polymorphous computing fabric, in: IEEE Micro, 2002, vol. 22, no 5, pp. 56–68.
[12]
C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Trans. on Design Automation of Elect. Syst., 2009, vol. 15, no 1, pp. 1–36.
http://doi.acm.org/10.1145/1640457.1640458
Publications of the year

Doctoral Dissertations and Habilitation Theses

[13]
A. Gammoudi.
Tasks scheduling and placement for reconfigurable architectures under energy constraint, Université de rennes 1 ; Université de Carthage (Tunisie), June 2018.
https://hal.inria.fr/tel-01956241
[14]
J. Luo.
Architectural and Protocol Exploration for 3D Optical Network-on-Chip, Université de Rennes 1 [UR1], July 2018.
https://hal.inria.fr/tel-01956255
[15]
V.-D. Pham.
Architectural Exploration of Network Interface for Energy Efficient 3D Optical Network-on-Chip, Université de rennes 1, December 2018.
https://hal.inria.fr/tel-01956229
[16]
R. Psiakis.
Performance Optimization Mechanisms for Fault-Resilient VLIW Processors, Université de Rennes 1, December 2018.
https://hal.inria.fr/tel-01956233
[17]
S. Rokicki.
Hardware Accelerated Dynamic Binary Translation, Université de Rennes 1 [UR1], December 2018.
https://hal.archives-ouvertes.fr/tel-01959136
[18]
M.-T. Tran.
Towards Hardware Synthesis of a Flexible Radio from a High-Level Language, Université de Rennes 1 [UR1], December 2018.
https://hal.inria.fr/tel-01942187

Articles in International Peer-Reviewed Journals

[19]
S.-I. Filip, Y. Nakatsukasa, L. N. Trefethen, B. Beckermann.
Rational Minimax Approximation via Adaptive Barycentric Representations, in: SIAM Journal on Scientific Computing, August 2018, vol. 40, no 4, pp. A2427-A2455, Author files.
https://hal.inria.fr/hal-01942974
[20]
A. Gammoudi, A. Benzina, M. Khalgui, D. Chillet.
Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multi-core Platforms, in: IEEE Transactions on Systems, Man, and Cybernetics: Systems, July 2018, pp. 1 - 14. [ DOI : 10.1109/TSMC.2018.2865965 ]
https://hal.inria.fr/hal-01934955
[21]
A. Kritikakou, T. Marty, M. Roy.
DYNASCORE: DYNAmic Software COntroller to increase REsource utilization in mixed-critical systems, in: ACM Transactions on Design Automation of Electronic Systems, January 2018, vol. 23, no 2, art ID n°13. [ DOI : 10.1145/3110222 ]
https://hal.archives-ouvertes.fr/hal-01559696
[22]
J. Luo, C. Killian, S. Le Beux, D. Chillet, O. Sentieys, I. O'Connor.
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects, in: ACM Journal on Emerging Technologies in Computing Systems, July 2018, vol. 14, no 2, pp. 1 - 19. [ DOI : 10.1145/3178453 ]
https://hal.inria.fr/hal-01934870
[23]
L. Mo, X. Cao, Y.-Q. Song, A. Kritikakou.
Distributed Node Coordination for Real-Time Energy-Constrained Control in Wireless Sensor and Actuator Networks, in: IEEE internet of things journal, May 2018, pp. 1-12. [ DOI : 10.1109/JIOT.2018.2839030 ]
https://hal.inria.fr/hal-01825524
[24]
L. Mo, A. Kritikakou, O. Sentieys.
Controllable QoS for Imprecise Computation Tasks on DVFS Multicores with Time and Energy Constraints, in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, July 2018, vol. 8, no 4, pp. 708-721. [ DOI : 10.1109/JETCAS.2018.2852005 ]
https://hal.inria.fr/hal-01831297
[25]
L. Mo, A. Kritikakou, O. Sentieys.
Energy-Quality-Time Optimized Task Mapping on DVFS-enabled Multicores, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2018, pp. 1 - 10. [ DOI : 10.1109/TCAD.2018.2857300 ]
https://hal.inria.fr/hal-01843918
[26]
T. H. Nguyen, P. Scalart, M. Gay, L. Bramerie, C. Peucheret, F. Gomez Agis, O. Sentieys, J.-C. Simon, M. Joindot.
New metric for IQ imbalance compensation in optical QPSK coherent systems, in: Photonic Network Communications, December 2018, vol. 36, no 3, pp. 326-337. [ DOI : 10.1007/s11107-018-0783-7 ]
https://hal.inria.fr/hal-01941892
[27]
S. Rokicki, E. Rohou, S. Derrien.
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2018, pp. 1-14. [ DOI : 10.1109/TCAD.2018.2864288 ]
https://hal.archives-ouvertes.fr/hal-01856163

International Conferences with Proceedings

[28]
N. Brisebarre, G. Constantinides, M. Ercegovac, S.-I. Filip, M. Istoan, J.-M. Muller.
A High Throughput Polynomial and Rational Function Approximations Evaluator, in: ARITH 2018 - 25th IEEE Symposium on Computer Arithmetic, Amherst, MA, United States, IEEE, June 2018, pp. 99-106. [ DOI : 10.1109/ARITH.2018.8464778 ]
https://hal.inria.fr/hal-01774364
[29]
A. Courtay, M. LE GENTIL, O. Berder, A. Carer, P. Scalart, O. Sentieys.
Zyggie: A Wireless Body Area Network platform for indoor positioning and motion tracking, in: ISCAS 2018 - IEEE International Symposium on Circuits and Systems, Florence, Italy, IEEE, May 2018, pp. 1-5. [ DOI : 10.1109/ISCAS.2018.8351278 ]
https://hal.archives-ouvertes.fr/hal-01804927
[30]
P. Dobias, E. Casseau, O. Sinnen.
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems, in: DASIP 2018 - Conference on Design and Architectures for Signal and Image Processing, Porto, Portugal, October 2018, pp. 1-7.
https://hal.inria.fr/hal-01942186
[31]
P. Dobias, E. Casseau, O. Sinnen.
Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems, in: SCOPES '18 - 21th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, May 2018, pp. 27-30. [ DOI : 10.1145/3207719.3207724 ]
https://hal.inria.fr/hal-01942185
[32]
A. Gammoudi, D. Chillet, M. Khalgui, A. Benzina.
Mapping of Periodic Tasks in Reconfigurable Heterogeneous Multi-core Platforms, in: ENASE 2018 - 13th International Conference on Evaluation of Novel Approaches to Software Engineering, Funchal, France, SCITEPRESS - Science and Technology Publications, March 2018, pp. 99-110. [ DOI : 10.5220/0006698500990110 ]
https://hal.inria.fr/hal-01936163
[33]
M. Gueguen, O. Sentieys, A. Termier.
Accelerating Itemset Sampling using Satisfiability Constraints on FPGA, in: DATE 2019 - IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, March 2019, pp. 1-6.
https://hal.inria.fr/hal-01941862
[34]
T. Lefeuvre, E. K. Kasnakli, I. Fassi, I. Puaut, C. Cullmann, S. Derrien, G. Gebhard.
Using Polyhedral Techniques to Tighten WCET Estimates of Optimized Code: A Case Study with Array Contraction, in: DATE 2018 - Design Automation and Test Europe, Dresden, Germany, IEEE, March 2018, pp. 925-930. [ DOI : 10.23919/DATE.2018.8342142 ]
https://hal.inria.fr/hal-01815499
[35]
J. Luo, V.-D. Pham, C. Killian, D. Chillet, I. O'Connor, O. Sentieys, S. LE BEUX.
Run-Time management of energy-performance trade-off in Optical Network-on-Chip, in: DCIS 2018 - XXXIII Conference on Design of Circuits and Integrated Systems, Lyon, France, November 2018, pp. 1-6.
https://hal.archives-ouvertes.fr/hal-01937350
[36]
T. Marty, T. Yuki, S. Derrien.
Enabling Overclocking with HLS Tools through Algorithm-Level Error Detection, in: FPT 2018 - International Conference on Field-Programmable Technology, Naha, Japan, December 2018.
https://hal.inria.fr/hal-01942429
[37]
L. Mo, A. Kritikakou, X. Cao.
Collaborative State Estimation and Actuator Scheduling for Cyber-Physical Systems under Random Multiple Events, in: AdHoc-Now 2018 - 17th International Conference on Ad Hoc Networks and Wireless, Saint Malo, France, Springer, September 2018, pp. 267-279. [ DOI : 10.1007/978-3-030-00247-3_24 ]
https://hal.inria.fr/hal-01857496
[38]
L. Mo, A. Kritikakou, O. Sentieys.
Energy-Quality-Time Optimized Task Mapping on DVFS-enabled Multicores, in: ESWEEK 2018 - Embedded Systems Week, Torino, Italy, September 2018, pp. 1-11.
https://hal.inria.fr/hal-01941764
[39]
L. Mo, A. Kritikakou, O. Sentieys.
Approximation-aware Task Deployment on Asymmetric Multicore Processors, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, March 2019, pp. 1-6.
https://hal.inria.fr/hal-01940358
[40]
R. Psiakis, A. Kritikakou, O. Sentieys.
Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units, in: DATE 2019 IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, March 2019, pp. 1-4.
https://hal.inria.fr/hal-01941860
[41]
I. Puaut, M. Dardaillon, C. Cullmann, G. Gebhard, S. Derrien.
Fine-Grain Iterative Compilation for WCET Estimation, in: WCET 2018 - 18th International Workshop on Worst-Case Execution Time Analysis, Barcelona, Spain, July 2018, pp. 1-12. [ DOI : 10.4230/OASIcs.WCET.2018.9 ]
https://hal.inria.fr/hal-01889944
[42]
S. Rokicki, E. Rohou, S. Derrien.
Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation, in: DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, IEEE, March 2018, pp. 1009-1014. [ DOI : 10.23919/DATE.2018.8342160 ]
https://hal.archives-ouvertes.fr/hal-01653110
[43]
S. Rokicki, E. Rohou, S. Derrien.
Aggressive Memory Speculation in HW/SW Co-Designed Machines, in: DATE 2019 - IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, March 2019.
https://hal.archives-ouvertes.fr/hal-01941876
[44]
M. Soltan Mohammadi, K. Cheshmi, M. Mehri Dehnavi, A. Venkat, T. Yuki, M. Mills Strout.
Extending Index-Array Properties for Data Dependence Analysis, in: LCPC 2018 - 31st International Workshop on Languages and Compilers for Parallel Computing, Salt Lake City, United States, October 2018.
https://hal.inria.fr/hal-01942363
[45]
J. O. Sosa, O. Sentieys, C. Roland.
A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment, in: Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, October 2018, pp. 1-8. [ DOI : 10.1109/NOCS.2018.8512165 ]
https://hal.inria.fr/hal-01941761

Conferences without Proceedings

[46]
A. Lucas.
A Simulator for Evaluating the Leakage in Arithmetic Circuits, in: CryptArchi 2018 - International Workshop on Cryptographic architectures embedded in logic devices, Lorient, France, June 2018, pp. 1-24.
https://hal.archives-ouvertes.fr/hal-01841048
[47]
A. Lucas, A. Tisserand.
Microcontroller Implementation of Simultaneous Protections Against Observation and Perturbation Attacks for ECC, in: SECRYPT: 15th International Conference on Security and Cryptography, Porto, Portugal, July 2018, pp. 1-8. [ DOI : 10.5220/0006884605700577 ]
https://hal.archives-ouvertes.fr/hal-01826303

Scientific Books (or Scientific Book chapters)

[48]
D. Menard, G. Caffarena, J. A. Lopez, D. Novo, O. Sentieys.
Fixed-point refinement of digital signal processing systems, in: Digitally Enhanced Mixed Signal Systems, 2018.
https://hal.inria.fr/hal-01941898
[49]
D. Menard, G. Caffarena, J. A. Lopez, D. Novo, O. Sentieys.
Analysis of Finite Word-Length Effects in Fixed-Point Systems, in: Handbook of Signal Processing Systems, S. S. Bhattacharyya (editor), 2019, pp. 1063-1101. [ DOI : 10.1007/978-3-319-91734-4_29 ]
https://hal.inria.fr/hal-01941888
[50]
L. Mo, A. Kritikakou, O. Sentieys.
Imprecise Computation Task Mapping on Multi-Core Wireless Sensor Networks, in: Encyclopedia of Wireless Networks, October 2018, pp. 1 - 6. [ DOI : 10.1007/978-3-319-32903-1_261-1 ]
https://hal.inria.fr/hal-01900174

Internal Reports

[51]
P. Iannetta, L. Gonnord, L. Morel, T. Yuki.
Semantic Array Dataflow Analysis, Inria Grenoble Rhône-Alpes, December 2018, no RR-9232.
https://hal.archives-ouvertes.fr/hal-01954396
[52]
T. Marty, T. Yuki, S. Derrien.
Algorithm Level Timing Speculation for Convolutional Neural Network Accelerators, Univ Rennes, Inria, CNRS, IRISA, France, June 2018, no RT-0500, pp. 1-17.
https://hal.inria.fr/hal-01811231
[53]
M. Soltan Mohammadi, K. Cheshmi, G. Gopalakrishnan, M. Hall, M. Mehri Dehnavi, A. Venkat, T. Yuki, M. Mills Strout.
Sparse Matrix Code Dependence Analysis Simplification at Compile Time, Arxiv, July 2018.
https://hal.inria.fr/hal-01942381

Other Publications

[54]
G. Berthou, A. Carer, H.-P. Charles, S. Derrien, K. Marquet, I. Miro-Panades, D. Pala, I. Puaut, F. Rastello, T. Risset, E. Rohou, G. Salagnac, O. Sentieys, B. Yarahmadi.
The Inria ZEP project: NVRAM and Harvesting for Zero Power Computations, March 2018, 10th Annual Non-Volatile Memories Workshop (NVMW), Poster.
https://hal.inria.fr/hal-01941766
[55]
A. Bosio, D. Menard, O. Sentieys.
A Comprehensive Analysis of Approximate Computing Techniques: From Component- to Application-Level, September 2018, pp. 1-2, ESWEEK 2018 - Embedded Systems Week.
https://hal.inria.fr/hal-01941755
[56]
A. Bosio, D. Menard, O. Sentieys.
A Comprehensive Analysis of Approximate Computing Techniques: From Component- to Application-Level, March 2019, DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe.
https://hal.inria.fr/hal-01941757
[57]
S.-I. Filip, A. Javeed, L. N. Trefethen.
Smooth random functions, random ODEs, and Gaussian processes, December 2018, To appear in SIAM Review.
https://hal.inria.fr/hal-01944992
[58]
N. Roux, B. Vrigneau, O. Sentieys.
Estimating Power Loads from Partial Appliance States, March 2018, NILM 2018 - 4th International Workshop on Non-Intrusive Load Monitoring, Poster.
https://hal.inria.fr/hal-01941877
[59]
O. Sentieys.
Playing with number representations and operator-level approximations, June 2018, Keynote at the Third Workshop on Approximate Computing (AxC), in conjunction with IEEE European Test Symposium (ETS).
https://hal.inria.fr/hal-01941868
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Compilation Approach for Coarse-Grained Reconfigurable Architectures, in: IEEE Design and Test of Computers, 2003, vol. 20, no 1, pp. 26-33.
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H. Lee, D. Nguyen, J.-E. Lee.
Optimizing Stream Program Performance on CGRA-based Systems, in: 52nd IEEE/ACM Design Automation Conference, 2015, pp. 110:1–110:6.
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Y. Park, H. Park, S. Mahlke.
CGRA express: accelerating execution using dynamic operation fusion, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'09, ACM, 2009, pp. 271–280.
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A reconfigurable fabric for accelerating large-scale datacenter services, in: ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), June 2014, pp. 13-24.
http://dx.doi.org/10.1109/ISCA.2014.6853195
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G. Theodoridis, D. Soudris, S. Vassiliadis.
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G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm, J. Hammes.
Automatic compilation to a coarse-grained reconfigurable system-on-chip, in: ACM Trans. on Emb. Comp. Syst., 2003, vol. 2, no 4, pp. 560–589.
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