Personnel
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Partnerships and Cooperations
Dissemination
Bibliography
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Bibliography

Major publications by the team in recent years
[1]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[2]
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
12, in: High-Level Synthesis From Algorithm to Digital Circuit, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.
http://dx.doi.org/10.1007/978-1-4020-8588-8
[3]
J.-M. Jézéquel, B. Combemale, S. Derrien, C. Guy, S. Rajopadhye.
Bridging the Chasm Between MDE and the World of Compilation, in: Journal of Software and Systems Modeling (SoSyM), October 2012, vol. 11, no 4, pp. 581-597. [ DOI : 10.1007/s10270-012-0266-8 ]
https://hal.inria.fr/hal-00717219
[4]
B. Le Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on VLSI Systems, 2008, vol. 16, no 11, pp. 1454-1464.
[5]
K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation, in: ACM transactions on Reconfigurable Technology and Systems (TRETS), June 2012, vol. 5, no 2, pp. 1-38.
http://doi.acm.org/10.1145/2209285.2209289
[6]
D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: Proc. ACM/IEEE CASES, October 2002.
[7]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13.
[8]
R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations, in: IEEE Transactions on Circuits and Systems. Part I, Regular Papers, October 2012, vol. 59, no 10, pp. 2326 - 2339. [ DOI : 10.1109/TCSI.2012.2188938 ]
http://hal.inria.fr/hal-00741741
[9]
C. Wolinski, M. Gokhale, K. McCabe.
A polymorphous computing fabric, in: IEEE Micro, 2002, vol. 22, no 5, pp. 56–68.
[10]
C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Trans. on Design Automation of Elect. Syst., 2009, vol. 15, no 1, pp. 1–36.
http://doi.acm.org/10.1145/1640457.1640458
Publications of the year

Doctoral Dissertations and Habilitation Theses

[11]
B. Barrois.
Methods to Evaluate Accuracy-Energy Trade-Off in Operator-Level Approximate Computing, Université de Rennes 1, December 2017.
https://hal.inria.fr/tel-01665015
[12]
G. Deest.
Implementation Trade-Offs for FGPA accelerators , Université de Rennes 1 [UR1], December 2017.
https://tel.archives-ouvertes.fr/tel-01665020
[13]
X.-C. Le.
Improving performance of non-intrusive load monitoring with low-cost sensor networks, Université Rennes 1, April 2017.
https://tel.archives-ouvertes.fr/tel-01622355
[14]
R. Ragavan.
Error handling and energy estimation for error resilient near-threshold computing, Université Rennes 1, September 2017.
https://tel.archives-ouvertes.fr/tel-01654476
[15]
R. Ragavan.
Error Handling and Energy Estimation Framework For Error Resilient Near-Threshold Computing, Rennes 1, September 2017.
https://hal.inria.fr/tel-01636803
[16]
B. Roux.
Methodology and Tools for Energy-aware Task Mapping on Heterogeneous Multiprocessor Architectures, Université de Rennes 1, November 2017.
https://hal.inria.fr/tel-01672814

Articles in International Peer-Reviewed Journals

[17]
A. Dorai, V. Fresse, C. Combes, E.-B. Bourennane, A. Mtibaa.
A collision management structure for NoC deployment on multi-FPGA, in: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), March 2017, vol. 49, pp. 28 - 43. [ DOI : 10.1016/j.micpro.2017.01.006 ]
https://hal-univ-bourgogne.archives-ouvertes.fr/hal-01484378
[18]
M. Fyrbiak, S. Rokicki, N. Bissantz, R. Tessier, C. Paar.
Hybrid Obfuscation to Protect against Disclosure Attacks on Embedded Microprocessors, in: IEEE Transactions on Computers, 2017.
https://hal.inria.fr/hal-01426565
[19]
A. Kritikakou, T. Marty, M. Roy.
DYNASCORE: DYNAmic Software COntroller to increase REsource utilization in mixed-critical systems, in: ACM Transactions on Design Automation of Electronic Systems (TODAES), September 2017, vol. 23, no 2, art ID n°13. [ DOI : 10.1145/3110222 ]
https://hal.archives-ouvertes.fr/hal-01559696
[20]
H. Li, S. Le Beux, M. J. Sepulveda Florez, I. O'Connor.
Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects, in: ACM Journal on Emerging Technologies in Computing Systems, July 2017, vol. XX.
https://hal.inria.fr/hal-01508192
[21]
T. H. Nguyen, M. Gay, F. Gomez Agis, S. Lobo, O. Sentieys, J.-C. Simon, C. Peucheret, L. Bramerie.
Impact of ADC parameters on linear optical sampling systems, in: Optics Communications, November 2017, vol. 402, pp. 362-367. [ DOI : 10.1016/j.optcom.2017.06.013 ]
https://hal.archives-ouvertes.fr/hal-01576164
[22]
T. H. Nguyen, P. Scalart, M. Gay, L. Bramerie, O. Sentieys, J.-C. Simon, C. Peucheret, M. Joindot.
Blind transmitter IQ imbalance compensation in M-QAM optical coherent systems, in: Journal of optical communications and networking, September 2017, vol. 9, no 9, pp. D42-D50. [ DOI : 10.1364/JOCN.9.000D42 ]
https://hal.archives-ouvertes.fr/hal-01573632
[23]
B. Rouxel, S. Derrien, I. Puaut.
Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures, in: ACM Transactions on Embedded Computing Systems (TECS), October 2017, vol. 16, no 5s, pp. 1 - 20. [ DOI : 10.1145/3126496 ]
https://hal.archives-ouvertes.fr/hal-01655383
[24]
C. Xiao, S. Wang, W. Liu, E. Casseau.
Parallel Custom Instruction Identification for Extensible Processors, in: Journal of Systems Architecture, May 2017, vol. 76, pp. 149-159. [ DOI : 10.1016/j.sysarc.2016.11.011 ]
https://hal.inria.fr/hal-01587020

International Conferences with Proceedings

[25]
L. Audrey, A. Tisserand.
ECC Protections against both Observation and Pertubation Attacks, in: CryptArchi 2017: 15th International Workshops on Cryptographic architectures embedded in logic devices, Smolenice, Slovakia, June 2017.
https://hal.archives-ouvertes.fr/hal-01545752
[26]
B. Barrois, O. Sentieys.
Customizing Fixed-Point and Floating-Point Arithmetic - A Case Study in K-Means Clustering, in: SiPS 2017 - IEEE International Workshop on Signal Processing Systems, Lorient, France, October 2017.
https://hal.inria.fr/hal-01633723
[27]
B. Barrois, O. Sentieys, D. Menard.
The Hidden Cost of Functional Approximation Against Careful Data Sizing – A Case Study, in: Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, France, 2017.
https://hal.inria.fr/hal-01423147
[28]
T. Bollengier, L. Lagadec, M. Najem, J.-C. Le Lann, P. Guilloux.
Soft timing closure for soft programmable logic cores: The ARGen approach , in: ARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft, Netherlands, Delft University of Technology , April 2017.
https://hal.archives-ouvertes.fr/hal-01475251
[29]
S. Cherubin, G. Agosta, I. Lasri, E. Rohou, O. Sentieys.
Implications of Reduced-Precision Computations in HPC: Performance, Energy and Error, in: International Conference on Parallel Computing (ParCo), Bologna, Italy, September 2017.
https://hal.inria.fr/hal-01633790
[30]
G. Deest, T. Yuki, S. Rajopadhye, S. Derrien.
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs, in: FPL - 27th International Conference on Field Programmable Logic and Applications, Gand, Belgium, IEEE, September 2017. [ DOI : 10.23919/FPL.2017.8056781 ]
https://hal.inria.fr/hal-01655590
[31]
S. Derrien, I. Puaut, P. Alefragis, M. Bednara, H. Bucher, C. David, Y. Debray, U. Durak, I. Fassi, C. Ferdinand, D. Hardy, A. Kritikakou, G. Rauwerda, S. Reder, M. Sicks, T. Stripf, K. Sunesen, T. Ter Braak, N. Voros, J. †. Becker.
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach, in: Design Automation and Test in Europe (DATE), 2017, Lausanne, Switzerland, March 2017, pp. 286 - 289. [ DOI : 10.23919/DATE.2017.7927000 ]
http://hal.upmc.fr/hal-01590418
[32]
A. Dorai, O. Sentieys, H. Dubois.
Evaluation of NoC on Multi-FPGA Interconnection Using GTX Transceiver, in: 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgia, December 2017.
https://hal.inria.fr/hal-01633785
[33]
A. H. EL MOUSSAWI, S. Derrien.
Superword Level Parallelism aware Word Length Optimization, in: Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, Switzerland, D. Atienza, G. D. Natale (editors), IEEE, March 2017.
https://hal.inria.fr/hal-01425550
[34]
G. Gallin, T. Ozlum Celik, A. Tisserand.
Architecture level Optimizations for Kummer based HECC on FPGAs, in: IndoCrypt 2017 - 18th International Conference on Cryptology in India, Chennai, India, International Conference in Cryptology in India : Progress in Cryptology – INDOCRYPT 2017, Springer, December 2017, vol. 10698, pp. 44-64. [ DOI : 10.1007/978-3-319-71667-1_3 ]
https://hal.archives-ouvertes.fr/hal-01614063
[35]
G. Gallin, A. Tisserand.
Hardware Architectures for HECC, in: CryptArchi 2017: 15th International Workshops on Cryptographic architectures embedded in logic devices, Smolenice, Slovakia, June 2017.
https://hal.archives-ouvertes.fr/hal-01545625
[36]
G. Gallin, A. Tisserand.
Hyper-Threaded Multiplier for HECC, in: Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, United States, IEEE, October 2017.
https://hal.archives-ouvertes.fr/hal-01620046
[37]
C. Killian, D. Chillet, S. Le Beux, O. Sentieys, V. D. Pham, I. O'Connor.
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques, in: DAC 2017 - IEEE/ACM Design Automation Conference DAC, Austin, United States, June 2017, 6 p.
https://hal.inria.fr/hal-01495468
[38]
R. Kumar Budhwani, R. Ragavan, O. Sentieys.
Taking Advantage of Correlation in Stochastic Computing, in: ISCAS 2017 - IEEE International Symposium on Circuits and Systems, Baltimore, United States, May 2017.
https://hal.inria.fr/hal-01633725
[39]
J. Luo, A. Elantably, D. D. Pham, C. Killian, D. Chillet, S. Le Beux, O. Sentieys, I. O'Connor.
Performance and Energy Aware Wavelength Allocation on Ring-Based WDM 3D Optical NoC, in: Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, Switzerland, March 2017.
https://hal.inria.fr/hal-01416958
[40]
L. Mo, A. Kritikakou, O. Sentieys.
Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores, in: 35th IEEE International Conference on Computer Design (ICCD), Boston, United States, IEEE, November 2017, 6 p.
https://hal.inria.fr/hal-01633782
[41]
R. Psiakis, A. Kritikakou, O. Sentieys.
NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors, in: ISVLSI 2017 - IEEE Computer Society Annual Symposium on VLSI, Bochum, Germany, May 2017, pp. 391-396. [ DOI : 10.1109/ISVLSI.2017.75 ]
https://hal.inria.fr/hal-01633770
[42]
R. Psiakis, A. Kritikakou, O. Sentieys.
Run-Time Instruction Replication for Permanent and Soft Error Mitigation in VLIW Processors, in: NEWCAS 2017 - 15th IEEE International New Circuits and Systems Conference, Strasbourg, France, June 2017, pp. 321-324. [ DOI : 10.1109/NEWCAS.2017.8010170 ]
https://hal.inria.fr/hal-01633778
[43]
R. Ragavan, B. Barrois, C. Killian, O. Sentieys.
Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications, in: Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, Switzerland, March 2017.
https://hal.archives-ouvertes.fr/hal-01417665
[44]
S. Rokicki, E. Rohou, S. Derrien.
Hardware-Accelerated Dynamic Binary Translation, in: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland, March 2017.
https://hal.inria.fr/hal-01423639
[45]
B. Rouxel, S. Derrien, I. Puaut.
Tightening contention delays while scheduling parallel applications on multi-core architectures, in: International Conference on Embedded Software (EMSOFT), 2017, Seoul, South Korea, International Conference on Embedded Software, October 2017, 20 p. [ DOI : 10.1145/3126496 ]
http://hal.upmc.fr/hal-01590508
[46]
Y. Uguen, F. de Dinechin, S. Derrien.
Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations, in: 27th International Conference on Field-Programmable Logic and Applications (FPL), Gent, Belgium, IEEE, September 2017, 8 p.
https://hal.inria.fr/hal-01373954
[47]
I. Wali, E. Casseau, A. Tisserand.
An Efficient Framework for Design and Assessment of Arithmetic Operators with Reduced-Precision Redundancy, in: Conference on Design and Architectures for Signal and Image Processing (DASIP), Dresden, Germany, September 2017.
https://hal.inria.fr/hal-01586983

National Conferences with Proceedings

[48]
D. P. Van, D. Chillet, C. Killian, O. Sentieys, S. Le Beux, I. O'Connor.
Electrical to Optical Interface for ONoC, in: GRETSI 2017 - XXVIème colloque, Juan les Pins, France, September 2017, pp. 1-4.
https://hal.inria.fr/hal-01655417

Conferences without Proceedings

[49]
G. Gallin, A. Tisserand.
Hardware Architectures Exploration for Hyper-Elliptic Curve Cryptography, in: Crypto'Puces 2017- 6ème rencontre Crypto'Puces, du composant au système communicant embarqué, Porquerolles, France, May 2017, 31 p.
https://hal.archives-ouvertes.fr/hal-01547034

Internal Reports

[50]
H. Yviquel, A. Sanchez, R. Mickaël, E. Casseau.
Multicore Runtime for Dynamic Dataflow Video Decoders, IETR/INSA Rennes ; IRISA, Inria Rennes, April 2017.
https://hal.archives-ouvertes.fr/hal-01503378

Other Publications

[51]
D. Chillet, D. P. Van, C. Killian, O. Sentieys, S. Le Beux, I. O'Connor.
Integration of an Optical NoC into multicore architecture, June 2017, pp. 1-2, 2017 - XIIème Colloque National du GDR SoC-SiP, Poster.
https://hal.inria.fr/hal-01655420
[52]
P. Dobias, E. Casseau, O. Sinnen.
Poster: Fault-Tolerant Multi-Processor Scheduling with Backup Copy Technique, September 2017, Conference on Design and Architectures for Signal and Image Processing (DASIP), Poster.
https://hal.inria.fr/hal-01610745
[53]
G. Gallin, A. Tisserand.
Finite Field Multiplier Architectures for Hyper-Elliptic Curve Cryptography, June 2017, Colloque National du GDR SOC2, Poster.
https://hal.archives-ouvertes.fr/hal-01539852
[54]
S. Rokicki, E. Rohou, S. Derrien.
Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation, December 2017, working paper or preprint.
https://hal.archives-ouvertes.fr/hal-01653110
[55]
Y. Uguen, F. de Dinechin, S. Derrien.
A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators, January 2017, working paper or preprint.
https://hal.archives-ouvertes.fr/hal-01498357
[56]
Y. Uguen, F. de Dinechin, S. Derrien.
High-Level Synthesis Using Application-Specific Arithmetic: A Case Study, April 2017, working paper or preprint.
https://hal.archives-ouvertes.fr/hal-01502644
References in notes
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REPLICA2Pro: Task Relocation by Bitstream Manipulation in Virtex-II/Pro FPGAs, in: 3rd Conference on Computing Frontiers (CF), 2006, pp. 403–412.
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Compilation Approach for Coarse-Grained Reconfigurable Architectures, in: IEEE Design and Test of Computers, 2003, vol. 20, no 1, pp. 26-33.
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Optimizing Stream Program Performance on CGRA-based Systems, in: 52nd IEEE/ACM Design Automation Conference, 2015, pp. 110:1–110:6.
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Y. Park, H. Park, S. Mahlke.
CGRA express: accelerating execution using dynamic operation fusion, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'09, ACM, 2009, pp. 271–280.
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A reconfigurable fabric for accelerating large-scale datacenter services, in: ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), June 2014, pp. 13-24.
http://dx.doi.org/10.1109/ISCA.2014.6853195
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G. Theodoridis, D. Soudris, S. Vassiliadis.
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