Members
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Partnerships and Cooperations
Dissemination
Bibliography
XML PDF e-pub
PDF e-Pub


Bibliography

Major publications by the team in recent years
[1]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[2]
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software, in: High-Level Synthesis From Algorithm to Digital Circuit, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.
http://dx.doi.org/10.1007/978-1-4020-8588-8
[3]
C. Guy, B. Combemale, S. Derrien, J. Steel, J.-M. Jézéquel.
On Model Subtyping, in: 8th European Conference on Modelling Foundations and Applications (ECMFA), Kgs. Lyngby, Denmark, July 2012.
http://hal.inria.fr/hal-00695034
[4]
C. Huriaux, A. Courtay, O. Sentieys.
Design Flow and Run-Time Management for Compressed FPGA Configurations, in: IEEE/ACM Design, Automation and Test in Europe (DATE), March 2015.
https://hal.inria.fr/hal-01089319
[5]
J.-M. Jézéquel, B. Combemale, S. Derrien, C. Guy, S. Rajopadhye.
Bridging the Chasm Between MDE and the World of Compilation, in: Journal of Software and Systems Modeling (SoSyM), October 2012, vol. 11, no 4, pp. 581-597. [ DOI : 10.1007/s10270-012-0266-8 ]
https://hal.inria.fr/hal-00717219
[6]
B. Le Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on VLSI Systems, 2008, vol. 16, no 11, pp. 1454-1464.
[7]
K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation, in: ACM transactions on Reconfigurable Technology and Systems (TRETS), June 2012, vol. 5, no 2, pp. 1-38.
http://doi.acm.org/10.1145/2209285.2209289
[8]
D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: Proc. ACM/IEEE CASES, October 2002.
[9]
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[10]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13.
[11]
R. Rocher, D. Ménard, O. Sentieys, P. Scalart.
Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations, in: IEEE Transactions on Circuits and Systems. Part I, Regular Papers, October 2012, vol. 59, no 10, pp. 2326 - 2339. [ DOI : 10.1109/TCSI.2012.2188938 ]
http://hal.inria.fr/hal-00741741
[12]
C. Wolinski, M. Gokhale, K. McCabe.
A polymorphous computing fabric, in: IEEE Micro, 2002, vol. 22, no 5, pp. 56–68.
[13]
C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Trans. on Design Automation of Elect. Syst., 2009, vol. 15, no 1, pp. 1–36.
http://doi.acm.org/10.1145/1640457.1640458
[14]
S. Wuliang, B. Combemale, S. Derrien, R. France.
Using Model Types to Support Contract-Aware Model Substitutability, in: 9th European Conference on Modelling Foundations and Applications (ECMFA), Montpellier, France, P. Van Gorp, T. Ritter, L. Rose (editors), LNCS, Springer-Verlag Berlin Heidelberg, 2013, vol. 7949, pp. 118-133. [ DOI : 10.1007/978-3-642-39013-5_9 ]
http://hal.inria.fr/hal-00808770
Publications of the year

Doctoral Dissertations and Habilitation Theses

[15]
F. Berthier.
Design of an ultra low power processor for wireless sensor nodes, Université de Rennes 1, France, December 2016.
https://hal.inria.fr/tel-01423146
[16]
A. H. EL MOUSSAWI.
SIMD-aware Word Length Optimization for Floating-point to Fixed-point Conversion targeting Embedded Processors, Universite de Rennes 1, December 2016.
https://hal.inria.fr/tel-01425642
[17]
J. Métairie.
Contributions to GF(2m) arithmetic operators for elliptic curve cryptography, Université Rennes 1, May 2016.
https://hal.archives-ouvertes.fr/tel-01324924
[18]
J. Métairie.
Contributions to GF(2m) Operators for Cryptographic Purposes, Université Rennes 1, May 2016.
https://tel.archives-ouvertes.fr/tel-01387919

Articles in International Peer-Reviewed Journals

[19]
M. M. Alam, E. Ben Hamida, O. Berder, O. Sentieys, D. Menard.
A Heuristic Self-Adaptive Medium Access Control for Resource-Constrained WBAN Systems, in: IEEE Access, April 2016, vol. 4, pp. 1287-1300.
https://hal.archives-ouvertes.fr/hal-01396104
[20]
F. Berthier, E. Beigne, F. HEITZMANN, O. Debicki, J.-F. Christmann, A. Valentian, O. Billoint, E. Amat, D. Morche, S. Chairat, O. Sentieys.
UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels, in: Solid-State Electronics, 2016, vol. 125, pp. 14 - 24. [ DOI : 10.1016/j.sse.2016.09.003 ]
https://hal.inria.fr/hal-01423144
[21]
K. Bigou, A. Tisserand.
Binary-Ternary Plus-Minus Modular Inversion in RNS, in: IEEE Transactions on Computers, November 2016, vol. 65, no 11, pp. 3495-3501. [ DOI : 10.1109/TC.2016.2529625 ]
https://hal.inria.fr/hal-01314268
[22]
R. Bonamy, S. Bilavarn, D. Chillet, O. Sentieys.
Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems, in: Journal of Low Power Electronics, September 2016, no September.
https://hal.archives-ouvertes.fr/hal-01345664
[23]
M. Fyrbiak, S. Rokicki, N. Bissantz, R. Tessier, C. Paar.
Hybrid Obfuscation to Protect against Disclosure Attacks on Embedded Microprocessors, in: IEEE Transactions on Computers, 2017.
https://hal.inria.fr/hal-01426565
[24]
V. Kelefouras, A. Kritikakou, I. Mporas, V. Kolonias.
A high performance Matrix-Matrix Multiplication Methodology for CPU and GPU architectures, in: Journal of Supercomputing, 2016, pp. 1-41. [ DOI : 10.1007/s11227-015-1613-7 ]
https://hal.archives-ouvertes.fr/hal-01255183
[25]
A. Kritikakou, F. Catthoor, V. Kelefouras, C. Goutis.
Array Size Computation under Uniform Overlapping and Irregular Accesses, in: ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016.
https://hal.archives-ouvertes.fr/hal-01239705
[26]
P. A. M. Oliveira, R. J. Cintra, F. M. Bayer, S. Kulasekera, A. Madanayake.
Low-complexity Image and Video Coding Based on an Approximate Discrete Tchebichef Transform, in: IEEE Transactions on Circuits and Systems for Video Technology, January 2016. [ DOI : 10.1109/TCSVT.2016.2515378 ]
https://hal.inria.fr/hal-01319513
[27]
L.-Q.-V. Tran, A. Didioui, C. Bernier, G. Vaumourin, F. Broekaert, A. Fritch.
Co-Simulating Complex Energy Harvesting WSN Applications: An In-Tunnel Wind Powered Monitoring Example, in: International Journal of Sensor Networks, 2016.
https://hal.inria.fr/hal-01264265
[28]
S. Wang, C. Xiao, W. Liu, E. Casseau.
A comparison of heuristic algorithms for custom instruction selection, in: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), August 2016, vol. 45, no A, 11 p.
https://hal.inria.fr/hal-01354991

Invited Conferences

[29]
O. Sentieys, J. Sepúlveda, S. Le Beux, J. Luo, C. Killian, D. Chillet, I. O 'connor, H. Li.
Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects, in: 2th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), co-located with IEEE/ACM Design Automation and Test in Europe (DATE’16), Dresden, Germany, March 2016.
https://hal.inria.fr/hal-01293506

International Conferences with Proceedings

[30]
B. Barrois, K. Parashar, O. Sentieys.
Leveraging Power Spectral Density for Scalable System-Level Accuracy Evaluation, in: IEEE/ACM Conference on Design Automation and Test in Europe (DATE), Dresden, Germany, March 2016, 6 p.
https://hal.inria.fr/hal-01253494
[31]
B. Barrois, O. Sentieys, D. Menard.
The Hidden Cost of Functional Approximation Against Careful Data Sizing – A Case Study, in: EEE/ACM Design Automation and Test in Europe (DATE), Lausanne, France, 2017.
https://hal.inria.fr/hal-01423147
[32]
K. Bigou, A. Tisserand.
Hybrid Position-Residues Number System, in: ARITH: 23rd Symposium on Computer Arithmetic, Santa Clara, CA, United States, J. Hormigo, S. Oberman, N. Revol (editors), IEEE, July 2016.
https://hal.inria.fr/hal-01314232
[33]
G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.
Towards Scalable and Efficient FPGA Stencil Accelerators, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, http://impact.gforge.inria.fr/, January 2016.
https://hal.inria.fr/hal-01254778
[34]
A. H. EL MOUSSAWI, S. Derrien.
Superword Level Parallelism aware Word Length Optimization, in: DATE - Design, Automation & Test in Europe Conference & Exhibition, Lausanne, Switzerland, D. Atienza, G. D. Natale (editors), IEEE, March 2017.
https://hal.inria.fr/hal-01425550
[35]
N. Estibals, G. Deest, A. El-Moussawi, S. Derrien.
System level synthesis for virtual memory enabled hardware threads, in: Design, Automation & Test in Europe Conference & Exhibition, Dresden, France, March 2016.
https://hal.inria.fr/hal-01424772
[36]
A. Gammoudi, A. Benzina, M. Khalgui, D. Chillet.
New Reconfigurable Middleware for Adaptive RTOS in Ubiquitous Devices, in: 10th International Conference on Mobile Ubiquitous Computing, Systems, Services and Technologies, Venise, Italy, October 2016.
https://hal.inria.fr/hal-01401716
[37]
A. Gammoudi, A. Benzina, M. Khalgui, D. Chillet.
Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms, in: 28th International Conference on Tools with Artificial Intelligence, San Jose, United States, November 2016.
https://hal.inria.fr/hal-01401712
[38]
A. Gammoudi, A. Benzina, M. Khalgui, D. Chillet, A. Goubaa.
Reconf-Pack: A Simulator for Reconfigurable Battery-Powered Real-Time Systems, in: 30th European Simulation and Modelling Conference, Las Palmas, Spain, October 2016.
https://hal.inria.fr/hal-01401706
[39]
C. Huriaux, O. Sentieys, R. Tessier.
Effects of I/O Routing through Column Interfaces in Embedded FPGA Fabrics, in: FPL - 26th International Conference on Field Programmable Logic and Applications, Lausanne, Switzerland, IEEE, August 2016.
https://hal.inria.fr/hal-01341156
[40]
J. Luo, A. Elantably, D. D. Pham, C. Killian, D. Chillet, S. Le Beux, O. Sentieys, I. O 'connor.
Performance and Energy Aware Wavelength Allocation on Ring-Based WDM 3D Optical NoC, in: Design, Automation & Test in Europe Conference & Exhibition (DATE) 2017, Lausanne, Switzerland, March 2017.
https://hal.inria.fr/hal-01416958
[41]
T.-H. Nguyen, P. Scalart, M. Gay, L. Bramerie, C. Peucheret, T. Nguyen-Ti, M. Gautier, O. Sentieys, J.-C. Simon, M. Joindot.
Blind Adaptive Transmitter IQ Imbalance Compensation in M-QAM Optical Coherent Systems, in: 2016 IEEE International Conference on Communication (ICC 2016), Kuala Lumpur, Malaysia, Communications (ICC), 2016 IEEE International Conference on, May 2016. [ DOI : 10.1109/ICC.2016.7510925 ]
https://hal.archives-ouvertes.fr/hal-01337225
[42]
T. H. Nguyen, P. Scalart, M. Gay, L. Bramerie, C. Peucheret, O. Sentieys, J.-C. Simon, M. Joindot.
Bi-harmonic decomposition-based maximum loglikelihood estimator for carrier phase estimation of coherent optical M-QAM, in: Optical Fiber Communication Conference (OFC 2016), Anaheim, CA, United States, Optical Fiber Communication Conference 2016, OSA (ISBN: 978-1-943580-07-1), March 2016, vol. DSP for Coherent Systems (Tu3K), Tu3K.3. [ DOI : 10.1364/OFC.2016.Tu3K.3 ]
https://hal.archives-ouvertes.fr/hal-01309175
[43]
R. Ragavan, B. Barrois, C. Killian, O. Sentieys.
Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications, in: Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, Switzerland, March 2017.
https://hal.archives-ouvertes.fr/hal-01417665
[44]
R. Ragavan, C. Killian, O. Sentieys.
Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window, in: ISVLSI, Pittsburgh, United States, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2016, pp. 325 - 330. [ DOI : 10.1109/ISVLSI.2016.13 ]
https://hal.inria.fr/hal-01416945
[45]
S. Rokicki, E. Rohou, S. Derrien.
Hardware-Accelerated Dynamic Binary Translation, in: IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland, March 2017.
https://hal.inria.fr/hal-01423639
[46]
B. Roux, M. Gautier, O. Sentieys, S. Derrien.
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architecture, in: IEEE 10th International Symposium on Embedded Multicore /Many-core Systems-on-Chip (MCSoC 2016), Lyon, France, September 2016.
https://hal.inria.fr/hal-01412835
[47]
M.-T. Tran, M. Gautier, E. Casseau.
On the FPGA-based implementation of a flexible waveform from a high-level description: Application to LTE FFT case study, in: EAI International Conference on Cognitive Radio Oriented Wireless Networks (Crowncom16), Grenoble, France, May 2016.
https://hal.inria.fr/hal-01302652

National Conferences with Proceedings

[48]
J. Luo, D. Chillet, C. Killian, S. Le Beux, I. O 'connor, O. Sentieys.
Crosstalk noise aware wavelength allocation in WDM 3D ONoC, in: Colloque National du GDR SoC-SiP, Nantes, France, June 2016.
https://hal.inria.fr/hal-01406355
[49]
J. Luo, D. Chillet, C. Killian, S. Le Beux, I. O 'connor, O. Sentieys.
Wavelength spacing optimization to reduce crosstalk in WDM 3D ONoC, in: Conférence d’informatique en Parallélisme, Architecture et Système, Lorient, France, July 2016.
https://hal.inria.fr/hal-01406341
[50]
V. D. Pham, D. Chillet, C. Killian, S. Le Beux, I. O 'connor, O. Sentieys.
Gestion de la consommation d'un ONoC intégré dans un MPSoC, in: Colloque National du GDR SoC-SiP, Nantes, France, June 2016.
https://hal.inria.fr/hal-01414341
[51]
V. D. Pham, C. Killian, D. Chillet, S. Le Beux, O. Sentieys, I. O 'connor.
Gestion de la consommation d'un réseau optique intégré dans un MPSoC, in: Conférence d’informatique en Parallélisme, Architecture et Système, Lorient, France, July 2016.
https://hal.inria.fr/hal-01406347
[52]
S. Rokicki, E. Rohou, S. Derrien.
Hybrid-JIT : Compilateur JIT Matériel/Logiciel pour les Processeurs VLIW Embarqués, in: Conférence d’informatique en Parallélisme, Architecture et Système (Compas), Lorient, France, July 2016.
https://hal.archives-ouvertes.fr/hal-01345306

Conferences without Proceedings

[53]
G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.
Towards Scalable and Efficient FPGA Stencil Accelerators, in: IMPACT'16, Prague, Czech Republic, January 2016.
https://hal.inria.fr/hal-01425018
[54]
A. Kritikakou, T. Marty, C. Pagetti, C. Rochange, M. Lauer, M. Roy.
Multiplexing Adaptive with Classic AUTOSAR? Adaptive Software Control to Increase Resource Utilization in Mixed-Critical Systems, in: Workshop CARS 2016 - Critical Automotive applications : Robustness & Safety, Göteborg, Sweden, CARS 2016 - Critical Automotive applications : Robustness & Safety, September 2016.
https://hal.archives-ouvertes.fr/hal-01375576

Patents

[55]
F. Berthier, E. Beigne, F. HEITZMANN, O. Debicki, O. Sentieys.
Cœur de processeur asynchrone et microcontrôleur de nœud de capteur communicant comportant un tel cœur de processeur, 2016, no 2016.
https://hal.inria.fr/hal-01423133

Other Publications

[56]
P. Guilloux, A. Tisserand.
Accurate Modeling of Fault Impact in Arithmetic Circuits, October 2016, DASIP: Conference on Design and Architectures for Signal and Image Processing (Demo Night), Poster.
https://hal.inria.fr/hal-01404772
[57]
P. Guilloux, A. Tisserand.
Plateforme matérielle–logicielle d'émulation de fautes pour des opérateurs arithmétiques, July 2016, 8 p, Compas 2016 : Conférence d’informatique en Parallélisme, Architecture et Système.
https://hal.inria.fr/hal-01313051
[58]
P. Guilloux, A. Tisserand.
Plateforme matérielle–logicielle à bas coût pour l'émulation de fautes, June 2016, Colloque du GDR SoC-SiP, Poster.
https://hal.inria.fr/hal-01346576
[59]
J. Luo, V. D. Pham, C. Killian, D. Chillet, S. Le Beux, I. O 'connor, O. Sentieys.
POSTER: Wavelength Allocation for Efficient Communications on Optical Network-on-Chip, October 2016, pp. 1656 - 1658, Conference on Design and Architectures for Signal and Image Processing, Poster. [ DOI : 10.1145/2810103.2810122 ]
https://hal.inria.fr/hal-01406328
[60]
O. Sentieys, D. Menard, K. Parashar, D. Novo.
Fixed-­point refinement, a guaranteed approach towards energy efficient computing, January 2016, Tutorial.
https://hal.inria.fr/hal-01423184
[61]
A. Tisserand, G. Gallin.
Hardware and Arithmetic for Hyperelliptic Curves Cryptography, November 2016, CominLabs Days 2016, Poster.
https://hal.inria.fr/hal-01404755
[62]
M.-T. Tran, E. Casseau, M. Gautier.
Demo abstract : FPGA-based implementation of a flexible FFT dedicated to LTE standard, October 2016, 2 p, Conference on Design and Architectures for Signal and Image Processing (DASIP), Demo Night, Poster.
https://hal.inria.fr/hal-01354992
[63]
Y. Uguen, F. de Dinechin, S. Derrien.
Arithmetic Optimizations for High-Level Synthesis, September 2016, working paper or preprint.
https://hal.inria.fr/hal-01373954
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CGRA express: accelerating execution using dynamic operation fusion, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'09, ACM, 2009, pp. 271–280.
http://doi.acm.org/10.1145/1629395.1629433
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