Members
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
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Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

[1]
Q. Colombet, F. Brandner, A. Darte.
Studying Optimal Spilling in the Light of SSA, in: ACM Transactions on Architecture and Code Optimization, January 2015, vol. 11-4, no 47, 26 p. [ DOI : 10.1145/2685392 ]
https://hal.inria.fr/hal-01099016

International Conferences with Proceedings

[2]
A. Cohen, A. Darte, P. Feautrier.
Static Analysis of OpenStream Programs, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, http://impact.gforge.inria.fr/, Michelle Strout and Tomofumi Yuki, January 2016.
https://hal.inria.fr/hal-01251845
[3]
A. Darte, A. Isoard.
Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes, in: 24th International Conference on Compiler Construction (CC'15), part of ETAPS'15, London, United Kingdom, April 2015.
https://hal.inria.fr/hal-01099017
[4]
A. Darte, A. Isoard, T. Yuki.
Liveness Analysis in Explicitly-Parallel Programs, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, Michelle Strout and Tomofumi Yuki, January 2016, http://impact.gforge.inria.fr/ .
https://hal.inria.fr/hal-01251843
[5]
G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.
Towards Scalable and Efficient FPGA Stencil Accelerators, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, January 2016, http://impact.gforge.inria.fr/ .
https://hal.inria.fr/hal-01254778
[6]
P. Feautrier.
The Power of Polynomials, in: 5th International Workshop on Polyhedral Compilation Techniques (IMPACT'15), Amsterdam, Netherlands, A. Jimborean, A. Darte (editors), January 2015.
https://hal.inria.fr/hal-01094787
[7]
L. Gonnord, D. Monniaux, G. Radanne.
Synthesis of ranking functions using extremal counterexamples, in: Programming Languages, Design and Implementation, Portland, Oregon, United States, June 2015. [ DOI : 10.1145/2737924.2737976 ]
https://hal.archives-ouvertes.fr/hal-01144622
[8]
T. Yuki.
Revisiting Loop Transformations with X10 Clocks, in: Proceedings of the ACM SIGPLAN Workshop on X10, Portland, OR, United States, June 2015. [ DOI : 10.1145/2771774.2771778 ]
https://hal.inria.fr/hal-01253630

Internal Reports

[9]
C. Alias, A. Plesco.
Data-aware Process Networks, Inria - Research Centre Grenoble – Rhône-Alpes ; Inria, June 2015, no RR-8735, 32 p.
https://hal.inria.fr/hal-01158726
[10]
A. Cohen, A. Darte, P. Feautrier.
Static Analysis of OpenStream Programs, CNRS ; Inria ; ENS Lyon, January 2016, no RR-8764, 26 p, Corresponding publication at IMPACT'16 (http://impact.gforge.inria.fr/impact2016 ).
https://hal.inria.fr/hal-01184408
[11]
A. Darte, A. Isoard.
Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes, LIP - ENS Lyon ; CNRS ; Inria ; UCBL, January 2015, no RR-8671, 28 p.
https://hal.inria.fr/hal-01103460
[12]
A. Darte, A. Isoard, T. Yuki.
Extended Lattice-Based Memory Allocation, CNRS ; ENS Lyon ; Inria, November 2015, no RR-8840, 31 p.
https://hal.inria.fr/hal-01251868
[13]
A. Darte, A. Isoard, T. Yuki.
Liveness Analysis in Explicitly-Parallel Programs, CNRS ; Inria ; ENS Lyon, January 2016, no RR-8839, 25 p, Corresponding publication at IMPACT'16 (http://impact.gforge.inria.fr/impact2016 ).
https://hal.inria.fr/hal-01251579
[14]
G. Iooss, S. Rajopadhye, C. Alias, Y. Zou.
Mono-parametric Tiling is a Polyhedral Transformation, Inria Grenoble - Rhône-Alpes ; CNRS, October 2015, no RR-8802, 40 p.
https://hal.inria.fr/hal-01219452
References in notes
[15]
C. Alias, A. Darte, P. Feautrier, L. Gonnord.
Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: 17th International Static Analysis Symposium (SAS'10), Perpignan, France, ACM press, September 2010, pp. 117-133.
[16]
C. Alias, A. Darte, P. Feautrier, L. Gonnord.
Rank: A Tool to Check Program Termination and Computational Complexity, in: International Workshop on Constraints in Software Testing Verification and Analysis (CSTVA'13), Luxembourg, March 2013, 238 p.
http://hal.inria.fr/hal-00801571
[17]
C. Alias, A. Darte, A. Plesco.
Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: International Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, March 2013, pp. 575-580.
[18]
Q. Colombet, F. Brandner, A. Darte.
Studying Optimal Spilling in the Light of SSA, in: International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, ACM, October 2011, pp. 25–34.
[19]
A. Darte, A. Isoard.
Parametric Tiling with Inter-Tile Data Reuse, in: 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, S. Rajopadhye, S. Verdoolaege (editors), January 2014.
https://hal.archives-ouvertes.fr/hal-00915831
[20]
A. Darte, R. Schreiber, G. Villard.
Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, pp. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
[21]
P. Feautrier.
Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, pp. 459–487.
[22]
P. Feautrier.
Simplification of Boolean Affine Formulas, Inria, July 2011, no RR-7689.
http://hal.inria.fr/inria-00609519/PDF/RR-7689.pdf
[23]
P. Feautrier.
Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, pp. 23–53.
[24]
P. Feautrier, A. Gamatié, L. Gonnord.
Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction, in: CSI Journal of Computing, 2012, vol. 1, no 4, 8:86 p.
[25]
A. Gamatié, L. Gonnord.
Static Analysis of Synchronous Programs in Signal for Efficient Design of Multi-Clocked Embedded Systems, in: International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'11), Chicago, USA, April 2011.
[26]
G. Iooss, S. Rajopadhye, C. Alias, Y. Zou.
CART: Constant Aspect Ratio Tiling, in: 4th International Workshop on Polyhedral Compilation Techniques (IMPACT’14), Vienna, Austria, S. Rajopadhye, S. Verdoolaege (editors), January 2014.
https://hal.archives-ouvertes.fr/hal-00915827
[27]
M. Maalej, L. Gonnord.
Do we still need new Alias Analyses?, Université Lyon Claude Bernard / Laboratoire d'Informatique du Parallélisme, November 2015, no RR-8812.
https://hal.inria.fr/hal-01228581
[28]
D. Monniaux, L. Gonnord.
An Encoding of Array Verification Problems into Array-Free Horn Clauses, July 2015, working paper or preprint.
https://hal.archives-ouvertes.fr/hal-01206882
[29]
H. Nazaré, I. Maffra, W. Santos, L. Oliveira, F. M. Q. Pereira, L. Gonnord.
Validation of Memory Accesses Through Symbolic Analyses, in: ACM International Conference on Object Oriented Programming Systems Languages & Applications (OOPSLA'14), Portland, Oregon, United States, October 2014, pp. 791-809.
https://hal.inria.fr/hal-01006209
[30]
V. Paisante, M. Maalej, L. Barbosa, L. Gonnord, F. M. Q. Pereira.
Symbolic Range Analysis of Pointers, in: International Symposium of Code Generation and Optmization (CGO'16), Barcelone, Spain, March 2016, pp. 791-809. [ DOI : 10.1145/2660193.2660205 ]
https://hal.inria.fr/hal-01228928
[31]
A. Pop, A. Cohen.
OpenStream: Expressiveness and data-flow compilation of OpenMP streaming programs, in: ACM Transactions on Architecture and Code Optimization (TACO), 2013, vol. 9, no 4, pp. 1-25.
[32]
A. Turjan, B. Kienhuis, E. Deprettere.
Translating Affine Nested-Loop Programs to Process Networks, in: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), New York, NY, USA, ACM, 2004, pp. 220–229.
[33]
S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.
Improved Derivation of Process Networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06), 2006.
[34]
T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.
Array Dataflow Analysis for Polyhedral X10 Programs, in: 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, ACM, 2013.
http://hal.inria.fr/hal-00761537
[35]
T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.
Checking Race Freedom of Clocked X10 Programs, arXiv, 2013, no arXiv.1311.4305.
http://hal.inria.fr/hal-00907723