Members
Overall Objectives
Research Program
Application Domains
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
XML PDF e-pub
PDF e-Pub


Bibliography

Major publications by the team in recent years
[1]
D. Chillet, A. Eiche, S. Pillement, O. Sentieys.
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network, in: Journal of Systems Architecture - Embedded Systems Design, April 2011, vol. 57, no 4, pp. 340-353.
http://dx.doi.org/10.1016/j.sysarc.2011.01.004
[2]
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, no 3.
[3]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, no 1, pp. 21-33.
[4]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[5]
S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, pp. 10–18, Best Paper Award.
[6]
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
12, in: High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.
http://dx.doi.org/10.1007/978-1-4020-8588-8
[7]
L. Imbert, A. Peirera, A. Tisserand.
A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, San Diego, California, U.S.A., F. T. Luk (editor), SPIE, August 2007, vol. 6697, no 66970N, pp. 1–9.
http://dx.doi.org/10.1117/12.733652
[8]
B. Le Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on Very Large Scale Integration Systems, November 2008, vol. 16, no 11, pp. 1454-1464.
[9]
K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system, in: Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, IEEE Computer Society, July 2009, pp. 145-152.
[10]
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, pp. 1–15.
[11]
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[12]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13, Article ID 562326, 13 pages.
[13]
C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, no 6.
[14]
A. Tisserand.
High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, no 1, pp. 14–23, invited paper.
http://dx.doi.org/10.1504/IJHPSA.2007.013288
[15]
C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Transactions on Design Automation of Electronic Systems, 2009, vol. 15, no 1, pp. 1–36.
http://doi.acm.org/10.1145/1640457.1640458
Publications of the year

Doctoral Dissertations and Habilitation Theses

[16]
K. Bigou.
Theoretical Study and Hardware Implementation of Arithmetical Units in Residue Number System (RNS) for Elliptic Curve Cryptography (ECC), Université Rennes 1, November 2014.
https://tel.archives-ouvertes.fr/tel-01084254
[17]
A. Chakhari.
Analytical accuracy evaluation of fixed-point systems for digital communication applications, Université de Rennes 1, October 2014.
https://hal.inria.fr/tel-01097176
[18]
A. Didioui.
Energy-Aware Transceiver for Energy Harvesting Wireless Sensor Networks, Université de Rennes 1, October 2014.
https://hal.inria.fr/tel-01099814
[19]
T. N. Le.
Global power management system for self-powered autonomous wireless sensor node, Université Rennes 1, July 2014.
https://tel.archives-ouvertes.fr/tel-01082861
[20]
T. N. Le.
Global Power Manager System for Self-Powered Autonomous Wireless Sensor Node, Université de Rennes 1, July 2014.
https://hal.inria.fr/tel-01099771
[21]
G. S. Ouedraogo.
Automatic Synthesis of Hardware Accelerators from High-Level Specifications of Physical Layers for Flexible Radio, Université de Rennes 1, December 2014.
https://hal.inria.fr/tel-01096012
[22]
M. Texier.
Dynamic Parallelism Management in Multi-Core Architectures for Mobile Systems, Université de Rennes 1, December 2014.
https://hal.inria.fr/tel-01099853
[23]
P. Udupa.
Low Complexity, Parallel Algorithms, and Scalable Architectures for Real Time Coherent Optical OFDM Systems, Université de Rennes 1, June 2014.
https://hal.inria.fr/tel-01099824

Articles in International Peer-Reviewed Journals

[24]
R. Bonamy, S. Bilavarn, D. Chillet, O. Sentieys.
Power Consumption Models for the Use of Dynamic and Partial Reconfiguration, in: Microprocessors and Microsystems, January 2014. [ DOI : 10.1016/j.micpro.2014.01.002 ]
https://hal.inria.fr/hal-00941532
[25]
L. Devaux, S. Pillement.
OCEAN, a flexible adaptive Network-on-Chip for dynamic applications, in: Microprocessors and Microsystems, 2014, forthcoming.
https://hal.archives-ouvertes.fr/hal-00944214
[26]
M. Djendi, P. Scalart.
Reducing over- and under-estimation of the a priori SNR in speech enhancement techniques, in: Digital Signal Processing, October 2014, no 32, 12 p. [ DOI : 10.1016/j.dsp.2014.05.007 ]
https://hal.inria.fr/hal-01100254
[27]
F. Guidec, D. Benferhat, P. Quinton.
Disruption-Tolerant Wireless Sensor Networking for Biomedical Monitoring in Outdoor Conditions, in: Mobile Networks and Applications, January 2014, vol. 19, no 6, pp. 684–697. [ DOI : 10.1007/s11036-013-0491-6 ]
https://hal.archives-ouvertes.fr/hal-00935862
[28]
S. M. A. H. Jafri, S. J. Piestrak, O. Sentieys, S. Pillement.
Design of the coarse-grained reconfigurable architecture DART with on-line error detection, in: Microprocessors and Microsystems, March 2014, vol. 38, no 2, pp. 124-136. [ DOI : 10.1016/j.micpro.2013.12.004 ]
https://hal.archives-ouvertes.fr/hal-00927376
[29]
J.-M. Kwadjane, B. Vrigneau, C. Langlais, Y. Cocheril, M. Berbineau.
Performance evaluation of max-dmin precoding in impulsive noise for train-to-wayside communications in subway tunnels, in: EURASIP Journal on Wireless Communications and Networking, May 2014, vol. 83. [ DOI : 10.1186/1687-1499-2014-83 ]
https://hal.archives-ouvertes.fr/hal-01009636
[30]
T. N. Le, A. Pegatoquet, O. Berder, O. Sentieys, A. Carer.
Energy Neutral Design Framework for Supercapacitor-based Autonomous Wireless Sensor Networks, in: ACM Journal on Emerging Technologies in Computing Systems, November 2014.
https://hal.archives-ouvertes.fr/hal-01069098
[31]
T. H. Nguyen, K. Lenglé, A. Bazin, L. Bramerie, C. Peucheret, M. Gay, O. Sentieys, J.-C. Simon, R. Raj, F. Raineri.
Phase-preserving power limiting function using InP on SOI photonic crystal nanocavity, in: IEEE Photonics Technology Letters, June 2014, vol. 26, no 12, pp. 1215-1218. [ DOI : 10.1109/LPT.2014.2319248 ]
https://hal.archives-ouvertes.fr/hal-01062994
[32]
G. S. Ouedraogo, M. Gautier, O. Sentieys.
A Frame-Based Domain-Specific Language for Rapid Prototyping of FPGA-Based Software Defined Radios, in: EURASIP Journal on Advances in Signal Processing, November 2014, 13 p. [ DOI : 10.1186/1687-6180-2014-164 ]
https://hal.inria.fr/hal-01084788
[33]
K. N. Parashar, D. Menard, O. Sentieys.
Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2014, vol. 33, no 4, pp. 599-612. [ DOI : 10.1109/TCAD.2013.2292510 ]
https://hal.inria.fr/hal-01097606
[34]
S. Piestrak.
A note on RNS architectures for the implementation of the diagonal function, in: Information Processing Letters, 2015, pp. 1-9.
https://hal.inria.fr/hal-01088395
[35]
C. Xiao, E. Casseau, S. Wang, W. Liu.
Automatic custom instruction identification for application-specific instruction set processors, in: Microprocessors and Microsystems - Embedded Hardware Design, November 2014, vol. 38, no Issue 8, Part B, 13 p. [ DOI : 10.1016/j.micpro.2014.09.001 ]
https://hal.inria.fr/hal-01098451
[36]
H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau.
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs, in: Journal of Signal Processing Systems, Springer, October 2014, pp. 1-16. [ DOI : 10.1007/s11265-014-0953-5 ]
https://hal.archives-ouvertes.fr/hal-01078142

Articles in National Peer-Reviewed Journals

[37]
P. Cotret, G. Gogniat.
Protection des architectures hétérogènes sur FPGA : une approche par pare-feux matériels, in: Techniques de l'Ingenieur, February 2014, 10 p, Référence IN175.
https://hal.inria.fr/hal-00866646
[38]
A. Tisserand.
Circuits électroniques pour la génération de nombres aléatoires, in: Techniques de l'ingénieur Technologies des composants, August 2014, no H5215.
https://hal.inria.fr/hal-01061471

International Conferences with Proceedings

[39]
K. Bigou, A. Tisserand.
RNS Modular Multiplication through Reduced Base Extensions, in: ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, Zurich, Switzerland, IEEE, June 2014, pp. 57-62. [ DOI : 10.1109/ASAP.2014.6868631 ]
https://hal.inria.fr/hal-01010961
[40]
J. Chen, A. Tisserand, E. Popovici, S. D. Cotofana.
Robust Sub-Powered Asynchronous Logic, in: PATMOS - International Workshop on Power And Timing Modeling, Optimization and Simulation, Palma de Mallorca, Spain, IEEE, September 2014. [ DOI : 10.1109/PATMOS.2014.6951863 ]
https://hal.inria.fr/hal-01063821
[41]
G. Deest, T. Yuki, O. Sentieys, S. Derrien.
Toward Scalable Source Level Accuracy Analysis for Floating-point to Fixed-point Conversion, in: 2014 IEEE/ACM International Conference on Computer-Aided Design, San Jose, United States, November 2014, pp. 726–733.
https://hal.inria.fr/hal-01095207
[42]
A. Didioui, C. Bernier, L.-Q.-V. Tran, O. Sentieys.
EnvAdapt: An Energy-Aware Simulation Framework for Power-Scalable Transceivers for Wireless Sensor Networks, in: 20th European Wireless Conference, Barcelona, Spain, May 2014, pp. 1-6.
https://hal.inria.fr/hal-01097062
[43]
J. Flocon-Cholet, J. Faure, A. Guérin, P. Scalart.
A robust howling detection algorithm based on a statistical approach, in: International Workshop on Acoustic Signal Enhancement (IWAENC), Antibes, France, September 2014.
https://hal.inria.fr/hal-01100273
[44]
J. Flocon-Cholet, A. Guérin, J. Faure, P. Scalart.
An investigation of temporal feature integration for a low-latency classification with application to speech/music/mix classification, in: 137th Audio Engineering Society Convention, no 9180, Los Angeles, United States, AES, October 2014.
https://hal.inria.fr/hal-01100261
[45]
M. Gautier, G. S. Ouedraogo, O. Sentieys.
Design Space Exploration in an FPGA-Based Software Defined Radio, in: Euromicro Conference on Digital System Design, Verona, Italy, August 2014. [ DOI : 10.1109/DSD.2014.44 ]
https://hal.inria.fr/hal-01084781
[46]
J. Heulot, M. Pelcat, J.-F. Nezan, Y. Oliva, S. Aridhi, S. S. Bhattacharyya.
Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems, in: GlobalSIP14, Atlanta, United States, December 2014.
https://hal.archives-ouvertes.fr/hal-01101790
[47]
C. Huriaux, A. Courtay, O. Sentieys.
Design Flow and Run-Time Management for Compressed FPGA Configurations, in: DATE - Design, Automation and Test in Europe, Grenoble, France, March 2015.
https://hal.inria.fr/hal-01089319
[48]
C. Huriaux, O. Sentieys, R. Tessier.
FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams, in: FPL - 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, IEEE, September 2014. [ DOI : 10.1109/FPL.2014.6927494 ]
https://hal.inria.fr/hal-01017184
[49]
L. Jiating, C. Killian, S. Le Beux, D. Chillet, H. Li, I. O'Connor, O. Sentieys.
Channel allocation protocol for reconfigurable Optical Network-on-Chip, in: SiPhotonics: Exploiting Silicon Photonics for energy-efficient high-performance computing (SiPhotonics'15), Amsterdam, Netherlands, January 2015, 7 p.
https://hal.inria.fr/hal-01096537
[50]
Q. H. Khuat, D. Chillet, M. Hubner.
Considering reconfiguration overhead in scheduling of dependent tasks on 2D Reconfigurable FPGA, in: International Conference on Adaptive Hardware Systems (AHS 2014), Leicester, United Kingdom, July 2014, 8 p.
https://hal.inria.fr/hal-01097496
[51]
Q. H. Khuat, D. Chillet, M. Hubner.
Dynamic Run-time Hardware/Software Scheduling For 3D Reconfigurable SoC, in: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 2014.
https://hal.inria.fr/hal-01097509
[52]
A. Kritikakou, C. Pagetti, M. Roy, C. Rochange, M. Faugère, S. Girbal, D. Gracia Pérez.
Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems, in: 22nd International Conference on Real-Time Networks and Systems, Versailles, France, October 2014. [ DOI : 10.1145/2659787.2659799 ]
https://hal.archives-ouvertes.fr/hal-01096102
[53]
Q. H. Le, E. Casseau, A. Courtay.
Place Reservation Technique for Online Task Placement on a Multi-context Heterogeneous Reconfigurable Architecture, in: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 2014, 6 p.
https://hal.inria.fr/hal-01076691
[54]
T. N. Le, A. Pegatoquet, O. Berder, O. Sentieys.
A Power Manager with Balanced Quality of Service for Energy-Harvesting Wireless Sensor Nodes, in: International Workshop on Energy Neutral Sensing Systems (ENSSys) - ACM SenSys Conference, Memphis, United States, November 2014, - p.
https://hal.archives-ouvertes.fr/hal-01069099
[55]
K. Martin, J.-P. Diguet, E. Casseau, Y. Oliva.
Dataflow program implementation onto a heterogeneous multiprocessor platform, in: METODO, Madrid, France, October 2014.
https://hal.archives-ouvertes.fr/hal-01075481
[56]
R. Masood, R. Burghelea, A. Carer, M. Le Gentil, O. Sentieys, P. Pajusco, C. Person, R. Sauleau.
Indoor Off-Body Channel Measurements using miniaturized Chip Antennas with Pattern Diversity, in: 44th European Microwave Conference (EuMC), Rome, Italy, October 2014.
https://hal.inria.fr/hal-01097608
[57]
V.-T. Nguyen, M. Gautier, O. Berder.
Implementation of an adaptive energy-efficient MAC protocol in OMNeT++/MiXiM, in: 1st OMNeT++ Community Summit, France, September 2014, pp. 1-4.
https://hal.archives-ouvertes.fr/hal-01070701
[58]
T. H. Nguyen, F. Gomez Agis, M. Gay, L. Anet Neto, P. Scalart, C. Peucheret, M. Joindot, O. Sentieys, J.-C. Simon, L. Bramerie.
IQ Imbalance Compensation Based on Maximum SNR Estimation in Coherent QPSK Systems, in: 16th International Conference on Transparent Optical Networks - ICTON, Graz, Austria, IEEE), July 2014, paper Tu.C1.3, ISBN : 978-1-4799-5600-5. [ DOI : 10.1109/ICTON.2014.6876406 ]
https://hal.archives-ouvertes.fr/hal-01062978
[59]
N.-Q. Nhan, M. Gautier, O. Berder.
Asynchronous MAC Protocol for Spectrum Agility in Wireless Body Area Sensor Networks, in: 9th International Conference on Cognitive Radio Oriented Wireless Networks, Oulu, Finland, June 2014, pp. 203-208.
https://hal.archives-ouvertes.fr/hal-01070543
[60]
G. S. Ouedraogo, M. Gautier, O. Sentieys.
Frame-based Modeling for Automatic Synthesis of FPGA-Software Defined Radio, in: 9th International Conference on Cognitive Radio Oriented Wireless Networks, Oulu, Finland, June 2014, pp. 203-208.
https://hal.archives-ouvertes.fr/hal-01070549
[61]
O. J. Oyedapo, B. Vrigneau, R. Vauzelle.
Cooperative Closed-loop MIMO Selective Transmissions in a HV Environment, in: SmartGridComm, Venice, Italy, November 2014.
https://hal.inria.fr/hal-01095692
[62]
C. Pham, P. Cousin, A. Carer.
Real-time On-Demand Multi-Hop Audio Streaming with Low-Resource Sensor Motes, in: IEEE SenseApp, in conjunction with LCN, Edmonton, Canada, 2014.
https://hal.archives-ouvertes.fr/hal-01093717
[63]
S. Rajhans, D. Chillet.
Intrinsic Fault Tolerance of Hopfield Model for Scheduling Technique in RSoC, in: International Conference on Neural Computing and Therory Application (NCTA 2014), Rome, Italy, October 2014.
https://hal.inria.fr/hal-01097500
[64]
L. Sadeghioon, P. Gavignet, A. Triki, J.-L. Barbey, E. Le Rouzic, L. Bramerie, V. Alaiwan, E. Borgne, C. Betoule, B. Arzur, A. Carer.
First experimental demonstration of real-time orchestration in a Multi-head metro network, in: 16th International Conference on Transparent Optical Networks (ICTON 2014), Graz, Austria, July 2014, pp. 1 - 4. [ DOI : 10.1109/ICTON.2014.6876667 ]
https://hal.archives-ouvertes.fr/hal-01084900
[65]
V. Tovinakere Dwarakanath, O. Sentieys, S. Derrien, C. Huriaux.
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes, in: FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, Boston, United States, IEEE, May 2014, pp. 230-233. [ DOI : 10.1109/FCCM.2014.68 ]
https://hal.inria.fr/hal-01017185
[66]
L.-Q.-V. Tran, O. Berder, O. Sentieys.
RIC-MAC: a MAC Protocol for Low-Power Cooperative Wireless Sensor Networks, in: IEEE Wireless Communications and Networking Conference (WCNC), Istanbul, Turkey, April 2014, pp. 1944-1949. [ DOI : 10.1109/WCNC.2014.6952567 ]
https://hal.inria.fr/hal-01097607
[67]
N. Veyrat-Charvillon, B. Gérard, F.-X. Standaert.
Soft Analytical Side-Channel Attacks, in: Advances in Cryptology - ASIACRYPT 2014 - 20th International Conference on the Theory and Application of Cryptology and Information Security, Kaoshiung, Taiwan, Springer, December 2014, vol. LNCS 8874, pp. 282 - 296. [ DOI : 10.1007/978-3-662-45611-8_15 ]
https://hal.inria.fr/hal-01096218
[68]
C. Xiao, E. Casseau.
Improving High-Level Synthesis Effectiveness Through Custom Operator Identification, in: IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.
https://hal.inria.fr/hal-00931036
[69]
H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau.
Efficient Software Synthesis of Dynamic Dataflow Programs, in: ICASSP 2014, Florence, Italy, May 2014, 1 p.
https://hal.archives-ouvertes.fr/hal-00988003

Conferences without Proceedings

[70]
F. Bucheron, A. Tisserand, L. Rilling.
Hardware/Software Support for Securing Virtualization in Embedded Systems, in: 1st Symposium on Digital Trust in Auvergne, Clermont-Ferrand, France, December 2014.
https://hal.inria.fr/hal-01095430

Scientific Books (or Scientific Book chapters)

[71]
M. Gautier, E. Casseau, H. Yviquel, G. S. Ouedraogo, M. Raulet, O. Sentieys.
Rapid Prototyping for Video Coding over Flexible Radio Links, in: Multimedia over Cognitive Radio Networks : Algorithms, Protocols, and Experiments, CRC Press, December 2014.
https://hal.inria.fr/hal-01095887
[72]
H. Yviquel, E. Casseau, M. Wipliez, J. Gorin, M. Raulet.
Classification-Based Optimization of Dynamic Dataflow Programs, in: Advancing Embedded Systems and Real-Time Communications with Emerging Technologies, IGI Global, 2014, pp. 282-301. [ DOI : 10.4018/978-1-4666-6034-2.ch012 ]
https://hal.archives-ouvertes.fr/hal-01068648

Patents

[73]
O. Sentieys, A. Courtay, C. Huriaux, S. Pillement.
Method and device for programming a FPGA, January 2014, no 14305143.1.
https://hal.inria.fr/hal-01099866

Other Publications

[74]
C. Huriaux, O. Sentieys, R. Tessier.
FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions, IEEE, May 2014, 30 p, FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines. [ DOI : 10.1109/FCCM.2014.17 ]
https://hal.inria.fr/hal-01100334
[75]
Q. H. Le, E. Casseau, A. Courtay.
Placement en Ligne de Tâches sur Architecture Dynamiquement Reconfigurable Hétérogène, June 2014, Colloque GDR SOC-SIP.
https://hal.inria.fr/hal-01061009
[76]
Y. Oliva, E. Casseau, K. Martin, P. Bomel, J.-P. Diguet, H. Yviquel, M. Raulet, E. Raffin, L. Morin.
Orcc's Compa-Backend demonstration, October 2014, Conference on Design and Architectures for Signal and Image Processing, Demo Night.
https://hal.inria.fr/hal-01059858
[77]
O. Sentieys, D. Menard, D. Novo, K. Parashar.
Automatic Fixed-Point Conversion: a Gateway to High-Level Power Optimization , March 2014, Tutorial at IEEE/ACM Design Automation and Test in Europe (DATE).
https://hal.inria.fr/hal-01100230
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[78]
S. Hauck, A. DeHon (editors)
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[79]
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MAC Essentials for Wireless Sensor Networks, in: Communications Surveys Tutorials, IEEE, quarter 2010, vol. 12, no 2, pp. 222 -248.
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[82]
V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.
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[83]
C. Bobda.
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[84]
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[85]
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A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.
[86]
M. Clark, M. Mulligan, D. Jackson, D. Linebarger.
Accelerating Fixed-Point Design for MB-OFDM UWB Systems, in: CommsDesign, 2005.
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[87]
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal minimum distance-based precoder for MIMO spatial multiplexing systems, in: IEEE Transactions on Signal Processing, 2004, vol. 52, no 3, pp. 617–627.
[88]
K. Compton, S. Hauck.
Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, no 2, pp. 171–210.
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[89]
G. Constantinides, P. Cheung, W. Luk.
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