Overall Objectives
Research Program
Application Domains
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
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Major publications by the team in recent years
D. Chillet, A. Eiche, S. Pillement, O. Sentieys.
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network, in: Journal of Systems Architecture - Embedded Systems Design, April 2011, vol. 57, no 4, pp. 340-353.
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, no 3.
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, no 1, pp. 21-33.
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, pp. 10–18, Best Paper Award.
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
12, in: High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.
L. Imbert, A. Peirera, A. Tisserand.
A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, San Diego, California, U.S.A., F. T. Luk (editor), SPIE, August 2007, vol. 6697, no 66970N, pp. 1–9.
B. Le Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on Very Large Scale Integration Systems, November 2008, vol. 16, no 11, pp. 1454-1464.
K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system, in: Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, IEEE Computer Society, July 2009, pp. 145-152.
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, pp. 1–15.
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13, Article ID 562326, 13 pages.
C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, no 6.
A. Tisserand.
High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, no 1, pp. 14–23, invited paper.
C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Transactions on Design Automation of Electronic Systems, 2009, vol. 15, no 1, pp. 1–36.
Publications of the year

Doctoral Dissertations and Habilitation Theses

K. Bigou.
Theoretical Study and Hardware Implementation of Arithmetical Units in Residue Number System (RNS) for Elliptic Curve Cryptography (ECC), Université Rennes 1, November 2014.
A. Chakhari.
Analytical accuracy evaluation of fixed-point systems for digital communication applications, Université de Rennes 1, October 2014.
A. Didioui.
Energy-Aware Transceiver for Energy Harvesting Wireless Sensor Networks, Université de Rennes 1, October 2014.
T. N. Le.
Global power management system for self-powered autonomous wireless sensor node, Université Rennes 1, July 2014.
T. N. Le.
Global Power Manager System for Self-Powered Autonomous Wireless Sensor Node, Université de Rennes 1, July 2014.
G. S. Ouedraogo.
Automatic Synthesis of Hardware Accelerators from High-Level Specifications of Physical Layers for Flexible Radio, Université de Rennes 1, December 2014.
M. Texier.
Dynamic Parallelism Management in Multi-Core Architectures for Mobile Systems, Université de Rennes 1, December 2014.
P. Udupa.
Low Complexity, Parallel Algorithms, and Scalable Architectures for Real Time Coherent Optical OFDM Systems, Université de Rennes 1, June 2014.

Articles in International Peer-Reviewed Journals

R. Bonamy, S. Bilavarn, D. Chillet, O. Sentieys.
Power Consumption Models for the Use of Dynamic and Partial Reconfiguration, in: Microprocessors and Microsystems, January 2014. [ DOI : 10.1016/j.micpro.2014.01.002 ]
L. Devaux, S. Pillement.
OCEAN, a flexible adaptive Network-on-Chip for dynamic applications, in: Microprocessors and Microsystems, 2014, forthcoming.
M. Djendi, P. Scalart.
Reducing over- and under-estimation of the a priori SNR in speech enhancement techniques, in: Digital Signal Processing, October 2014, no 32, 12 p. [ DOI : 10.1016/j.dsp.2014.05.007 ]
F. Guidec, D. Benferhat, P. Quinton.
Disruption-Tolerant Wireless Sensor Networking for Biomedical Monitoring in Outdoor Conditions, in: Mobile Networks and Applications, January 2014, vol. 19, no 6, pp. 684–697. [ DOI : 10.1007/s11036-013-0491-6 ]
S. M. A. H. Jafri, S. J. Piestrak, O. Sentieys, S. Pillement.
Design of the coarse-grained reconfigurable architecture DART with on-line error detection, in: Microprocessors and Microsystems, March 2014, vol. 38, no 2, pp. 124-136. [ DOI : 10.1016/j.micpro.2013.12.004 ]
J.-M. Kwadjane, B. Vrigneau, C. Langlais, Y. Cocheril, M. Berbineau.
Performance evaluation of max-dmin precoding in impulsive noise for train-to-wayside communications in subway tunnels, in: EURASIP Journal on Wireless Communications and Networking, May 2014, vol. 83. [ DOI : 10.1186/1687-1499-2014-83 ]
T. N. Le, A. Pegatoquet, O. Berder, O. Sentieys, A. Carer.
Energy Neutral Design Framework for Supercapacitor-based Autonomous Wireless Sensor Networks, in: ACM Journal on Emerging Technologies in Computing Systems, November 2014.
T. H. Nguyen, K. Lenglé, A. Bazin, L. Bramerie, C. Peucheret, M. Gay, O. Sentieys, J.-C. Simon, R. Raj, F. Raineri.
Phase-preserving power limiting function using InP on SOI photonic crystal nanocavity, in: IEEE Photonics Technology Letters, June 2014, vol. 26, no 12, pp. 1215-1218. [ DOI : 10.1109/LPT.2014.2319248 ]
G. S. Ouedraogo, M. Gautier, O. Sentieys.
A Frame-Based Domain-Specific Language for Rapid Prototyping of FPGA-Based Software Defined Radios, in: EURASIP Journal on Advances in Signal Processing, November 2014, 13 p. [ DOI : 10.1186/1687-6180-2014-164 ]
K. N. Parashar, D. Menard, O. Sentieys.
Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2014, vol. 33, no 4, pp. 599-612. [ DOI : 10.1109/TCAD.2013.2292510 ]
S. Piestrak.
A note on RNS architectures for the implementation of the diagonal function, in: Information Processing Letters, 2015, pp. 1-9.
C. Xiao, E. Casseau, S. Wang, W. Liu.
Automatic custom instruction identification for application-specific instruction set processors, in: Microprocessors and Microsystems - Embedded Hardware Design, November 2014, vol. 38, no Issue 8, Part B, 13 p. [ DOI : 10.1016/j.micpro.2014.09.001 ]
H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau.
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs, in: Journal of Signal Processing Systems, Springer, October 2014, pp. 1-16. [ DOI : 10.1007/s11265-014-0953-5 ]

Articles in National Peer-Reviewed Journals

P. Cotret, G. Gogniat.
Protection des architectures hétérogènes sur FPGA : une approche par pare-feux matériels, in: Techniques de l'Ingenieur, February 2014, 10 p, Référence IN175.
A. Tisserand.
Circuits électroniques pour la génération de nombres aléatoires, in: Techniques de l'ingénieur Technologies des composants, August 2014, no H5215.

International Conferences with Proceedings

K. Bigou, A. Tisserand.
RNS Modular Multiplication through Reduced Base Extensions, in: ASAP - 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, Zurich, Switzerland, IEEE, June 2014, pp. 57-62. [ DOI : 10.1109/ASAP.2014.6868631 ]
J. Chen, A. Tisserand, E. Popovici, S. D. Cotofana.
Robust Sub-Powered Asynchronous Logic, in: PATMOS - International Workshop on Power And Timing Modeling, Optimization and Simulation, Palma de Mallorca, Spain, IEEE, September 2014. [ DOI : 10.1109/PATMOS.2014.6951863 ]
G. Deest, T. Yuki, O. Sentieys, S. Derrien.
Toward Scalable Source Level Accuracy Analysis for Floating-point to Fixed-point Conversion, in: 2014 IEEE/ACM International Conference on Computer-Aided Design, San Jose, United States, November 2014, pp. 726–733.
A. Didioui, C. Bernier, L.-Q.-V. Tran, O. Sentieys.
EnvAdapt: An Energy-Aware Simulation Framework for Power-Scalable Transceivers for Wireless Sensor Networks, in: 20th European Wireless Conference, Barcelona, Spain, May 2014, pp. 1-6.
J. Flocon-Cholet, J. Faure, A. Guérin, P. Scalart.
A robust howling detection algorithm based on a statistical approach, in: International Workshop on Acoustic Signal Enhancement (IWAENC), Antibes, France, September 2014.
J. Flocon-Cholet, A. Guérin, J. Faure, P. Scalart.
An investigation of temporal feature integration for a low-latency classification with application to speech/music/mix classification, in: 137th Audio Engineering Society Convention, no 9180, Los Angeles, United States, AES, October 2014.
M. Gautier, G. S. Ouedraogo, O. Sentieys.
Design Space Exploration in an FPGA-Based Software Defined Radio, in: Euromicro Conference on Digital System Design, Verona, Italy, August 2014. [ DOI : 10.1109/DSD.2014.44 ]
J. Heulot, M. Pelcat, J.-F. Nezan, Y. Oliva, S. Aridhi, S. S. Bhattacharyya.
Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems, in: GlobalSIP14, Atlanta, United States, December 2014.
C. Huriaux, A. Courtay, O. Sentieys.
Design Flow and Run-Time Management for Compressed FPGA Configurations, in: DATE - Design, Automation and Test in Europe, Grenoble, France, March 2015.
C. Huriaux, O. Sentieys, R. Tessier.
FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams, in: FPL - 24th International Conference on Field Programmable Logic and Applications, Munich, Germany, IEEE, September 2014. [ DOI : 10.1109/FPL.2014.6927494 ]
L. Jiating, C. Killian, S. Le Beux, D. Chillet, H. Li, I. O'Connor, O. Sentieys.
Channel allocation protocol for reconfigurable Optical Network-on-Chip, in: SiPhotonics: Exploiting Silicon Photonics for energy-efficient high-performance computing (SiPhotonics'15), Amsterdam, Netherlands, January 2015, 7 p.
Q. H. Khuat, D. Chillet, M. Hubner.
Considering reconfiguration overhead in scheduling of dependent tasks on 2D Reconfigurable FPGA, in: International Conference on Adaptive Hardware Systems (AHS 2014), Leicester, United Kingdom, July 2014, 8 p.
Q. H. Khuat, D. Chillet, M. Hubner.
Dynamic Run-time Hardware/Software Scheduling For 3D Reconfigurable SoC, in: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 2014.
A. Kritikakou, C. Pagetti, M. Roy, C. Rochange, M. Faugère, S. Girbal, D. Gracia Pérez.
Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems, in: 22nd International Conference on Real-Time Networks and Systems, Versailles, France, October 2014. [ DOI : 10.1145/2659787.2659799 ]
Q. H. Le, E. Casseau, A. Courtay.
Place Reservation Technique for Online Task Placement on a Multi-context Heterogeneous Reconfigurable Architecture, in: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 2014, 6 p.
T. N. Le, A. Pegatoquet, O. Berder, O. Sentieys.
A Power Manager with Balanced Quality of Service for Energy-Harvesting Wireless Sensor Nodes, in: International Workshop on Energy Neutral Sensing Systems (ENSSys) - ACM SenSys Conference, Memphis, United States, November 2014, - p.
K. Martin, J.-P. Diguet, E. Casseau, Y. Oliva.
Dataflow program implementation onto a heterogeneous multiprocessor platform, in: METODO, Madrid, France, October 2014.
R. Masood, R. Burghelea, A. Carer, M. Le Gentil, O. Sentieys, P. Pajusco, C. Person, R. Sauleau.
Indoor Off-Body Channel Measurements using miniaturized Chip Antennas with Pattern Diversity, in: 44th European Microwave Conference (EuMC), Rome, Italy, October 2014.
V.-T. Nguyen, M. Gautier, O. Berder.
Implementation of an adaptive energy-efficient MAC protocol in OMNeT++/MiXiM, in: 1st OMNeT++ Community Summit, France, September 2014, pp. 1-4.
T. H. Nguyen, F. Gomez Agis, M. Gay, L. Anet Neto, P. Scalart, C. Peucheret, M. Joindot, O. Sentieys, J.-C. Simon, L. Bramerie.
IQ Imbalance Compensation Based on Maximum SNR Estimation in Coherent QPSK Systems, in: 16th International Conference on Transparent Optical Networks - ICTON, Graz, Austria, IEEE), July 2014, paper Tu.C1.3, ISBN : 978-1-4799-5600-5. [ DOI : 10.1109/ICTON.2014.6876406 ]
N.-Q. Nhan, M. Gautier, O. Berder.
Asynchronous MAC Protocol for Spectrum Agility in Wireless Body Area Sensor Networks, in: 9th International Conference on Cognitive Radio Oriented Wireless Networks, Oulu, Finland, June 2014, pp. 203-208.
G. S. Ouedraogo, M. Gautier, O. Sentieys.
Frame-based Modeling for Automatic Synthesis of FPGA-Software Defined Radio, in: 9th International Conference on Cognitive Radio Oriented Wireless Networks, Oulu, Finland, June 2014, pp. 203-208.
O. J. Oyedapo, B. Vrigneau, R. Vauzelle.
Cooperative Closed-loop MIMO Selective Transmissions in a HV Environment, in: SmartGridComm, Venice, Italy, November 2014.
C. Pham, P. Cousin, A. Carer.
Real-time On-Demand Multi-Hop Audio Streaming with Low-Resource Sensor Motes, in: IEEE SenseApp, in conjunction with LCN, Edmonton, Canada, 2014.
S. Rajhans, D. Chillet.
Intrinsic Fault Tolerance of Hopfield Model for Scheduling Technique in RSoC, in: International Conference on Neural Computing and Therory Application (NCTA 2014), Rome, Italy, October 2014.
L. Sadeghioon, P. Gavignet, A. Triki, J.-L. Barbey, E. Le Rouzic, L. Bramerie, V. Alaiwan, E. Borgne, C. Betoule, B. Arzur, A. Carer.
First experimental demonstration of real-time orchestration in a Multi-head metro network, in: 16th International Conference on Transparent Optical Networks (ICTON 2014), Graz, Austria, July 2014, pp. 1 - 4. [ DOI : 10.1109/ICTON.2014.6876667 ]
V. Tovinakere Dwarakanath, O. Sentieys, S. Derrien, C. Huriaux.
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes, in: FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, Boston, United States, IEEE, May 2014, pp. 230-233. [ DOI : 10.1109/FCCM.2014.68 ]
L.-Q.-V. Tran, O. Berder, O. Sentieys.
RIC-MAC: a MAC Protocol for Low-Power Cooperative Wireless Sensor Networks, in: IEEE Wireless Communications and Networking Conference (WCNC), Istanbul, Turkey, April 2014, pp. 1944-1949. [ DOI : 10.1109/WCNC.2014.6952567 ]
N. Veyrat-Charvillon, B. Gérard, F.-X. Standaert.
Soft Analytical Side-Channel Attacks, in: Advances in Cryptology - ASIACRYPT 2014 - 20th International Conference on the Theory and Application of Cryptology and Information Security, Kaoshiung, Taiwan, Springer, December 2014, vol. LNCS 8874, pp. 282 - 296. [ DOI : 10.1007/978-3-662-45611-8_15 ]
C. Xiao, E. Casseau.
Improving High-Level Synthesis Effectiveness Through Custom Operator Identification, in: IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.
H. Yviquel, A. Sanchez, P. Jääskeläinen, J. Takala, M. Raulet, E. Casseau.
Efficient Software Synthesis of Dynamic Dataflow Programs, in: ICASSP 2014, Florence, Italy, May 2014, 1 p.

Conferences without Proceedings

F. Bucheron, A. Tisserand, L. Rilling.
Hardware/Software Support for Securing Virtualization in Embedded Systems, in: 1st Symposium on Digital Trust in Auvergne, Clermont-Ferrand, France, December 2014.

Scientific Books (or Scientific Book chapters)

M. Gautier, E. Casseau, H. Yviquel, G. S. Ouedraogo, M. Raulet, O. Sentieys.
Rapid Prototyping for Video Coding over Flexible Radio Links, in: Multimedia over Cognitive Radio Networks : Algorithms, Protocols, and Experiments, CRC Press, December 2014.
H. Yviquel, E. Casseau, M. Wipliez, J. Gorin, M. Raulet.
Classification-Based Optimization of Dynamic Dataflow Programs, in: Advancing Embedded Systems and Real-Time Communications with Emerging Technologies, IGI Global, 2014, pp. 282-301. [ DOI : 10.4018/978-1-4666-6034-2.ch012 ]


O. Sentieys, A. Courtay, C. Huriaux, S. Pillement.
Method and device for programming a FPGA, January 2014, no 14305143.1.

Other Publications

C. Huriaux, O. Sentieys, R. Tessier.
FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions, IEEE, May 2014, 30 p, FCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines. [ DOI : 10.1109/FCCM.2014.17 ]
Q. H. Le, E. Casseau, A. Courtay.
Placement en Ligne de Tâches sur Architecture Dynamiquement Reconfigurable Hétérogène, June 2014, Colloque GDR SOC-SIP.
Y. Oliva, E. Casseau, K. Martin, P. Bomel, J.-P. Diguet, H. Yviquel, M. Raulet, E. Raffin, L. Morin.
Orcc's Compa-Backend demonstration, October 2014, Conference on Design and Architectures for Signal and Image Processing, Demo Night.
O. Sentieys, D. Menard, D. Novo, K. Parashar.
Automatic Fixed-Point Conversion: a Gateway to High-Level Power Optimization , March 2014, Tutorial at IEEE/ACM Design Automation and Test in Europe (DATE).
References in notes
S. Hauck, A. DeHon (editors)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann, 2008.
Z. Alliance.
Zigbee specification, ZigBee Alliance, 2005, no ZigBee Document 053474r06, Version.
A. Bachir, M. Dohler, T. Watteyne, K. Leung.
MAC Essentials for Wireless Sensor Networks, in: Communications Surveys Tutorials, IEEE, quarter 2010, vol. 12, no 2, pp. 222 -248.
F. Barat, M. Jayapala, T. Vander Aa, R. Lauwereins, G. Deconinck, H. Corporaal.
Low Power Coarse-Grained Reconfigurable Instruction Set Processor, in: International Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science, September 2003, pp. 230–239.
V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.
PACT XPP — A Self-Reconfigurable Data Processing Architecture, in: The Journal of Supercomputing, 2003, vol. 26, no 2, pp. 167–184.
C. Bobda.
Introduction to Reconfigurable Computing: Architectures Algorithms and Applications, Springer, 2007.
J. M. P. Cardoso, P. C. Diniz, M. Weinhardt.
Compiling for reconfigurable computing: A survey, in: ACM Comput. Surv., June 2010, vol. 42, 13:1 p.
D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.
M. Clark, M. Mulligan, D. Jackson, D. Linebarger.
Accelerating Fixed-Point Design for MB-OFDM UWB Systems, in: CommsDesign, 2005.
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal minimum distance-based precoder for MIMO spatial multiplexing systems, in: IEEE Transactions on Signal Processing, 2004, vol. 52, no 3, pp. 617–627.
K. Compton, S. Hauck.
Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, no 2, pp. 171–210.
G. Constantinides, P. Cheung, W. Luk.
Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, no 10, pp. 1432- 1442.
M. Coors, H. Keding, O. Luthje, H. Meyr.
Fast Bit-True Simulation, in: Proc. ACM/IEEE Design Automation Conference (DAC), Las Vegas, june 2001, pp. 708-713.
S. Cui, A. Goldsmith, A. Bahai.
Energy-efficiency of MIMO and cooperative MIMO techniques in sensor networks, in: IEEE Journal on Selected Areas in Communications, 2004, vol. 22, no 6, pp. 1089–1098.
K. Danne, R. Muhlenbernd, M. Platzner.
Executing hardware tasks on dynamically reconfigurable devices under real-time conditions, in: International Conference on Field Programmable Logic and Applications, Lecture Notes in Computer Science, 2006.
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
M. Dohler, E. Lefranc, H. Aghvami.
Space-time block codes for virtual antenna arrays, in: The 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 2002, vol. 1.
A. Dunkels, B. Gronvall, T. Voigt.
Contiki-a lightweight and flexible operating system for tiny networked sensors, in: Proceedings of the First IEEE Workshop on Embedded Networked Sensors, 2004.
P. Faraboshi, G. Brown, J. Fisher, G. Desoli.
Lx: A technology Platform for Customizable VLIW Embedded Processing, in: ACM/IEEE Int. Symp. on Computer Architecture (ISCA 00), Vancouver, Canada, June 2000, pp. 203–213.
P. Garcia, K. Compton, M. Schulte, E. Blem, W. Fu.
An overview of reconfigurable hardware in embedded systems, in: EURASIP J. Embedded Syst., January 2006, vol. 2006, pp. 1–19.
S. Hauck, A. DeHon.
Reconfigurable computing: the theory and practice of FPGA-based computation, Series on Systems on Silicon, Morgan Kaufmann, 2008.
A. Hormati, M. Kudlur, S. Mahlke, D. Bacon, R. Rabbah.
Optimus: efficient realization of streaming applications on FPGAs, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'08, ACM, 2008, pp. 41–50.
S. Kim, W. Sung.
Word-length optimization for high level synthesis of digital signal processing systems, in: IEEE Workshop on Signal Processing Systems, Boston, October 1998, pp. 142-151.
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, September 2000, vol. 47, no 9, pp. 840-848.
J. Laneman, G. Wornell.
Distributed space-time-coded protocols for exploiting cooperative diversity in wireless networks, in: IEEE Transactions on Information Theory, 2003, vol. 49, no 10, pp. 2415–2425.
A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, R. Guerrieri.
A VLIW Processor With Reconfigurable Instruction Set for Embedded Applications, in: IEEE J. of Solid-State Circuits, 2003, vol. 38, no 11, pp. 1876–1886.
T. Marescaux, V. Nollet, J. Mignolet, A. Bartica, W. Moffata, P. Avasarea, P. Coenea, D. Verkest, S. Vernalde, R. Lauwereins.
Run-time support for heterogeneous multitasking on reconfigurable SoCs, in: Integration, the VLSI journal, 2004, vol. 38, pp. 107–130.
B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins.
ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix, in: Proc. Int. Conf. on Field Programmable Logic and Applications, Springer, 2003, pp. 61–70.
D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: IEEE/ACM Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Grenoble, October 2002.
H. Nikolov, M. Thompson, T. Stefanov, A. Pimentel, S. Polstra, R. Bose, C. Zissulescu, E. Deprettere.
Daedalus: toward composable multimedia MP-SoC design, in: Proc. Design Automation Conference, New York, NY, USA, DAC'08, ACM, 2008, pp. 574–579.
Y. Park, H. Park, S. Mahlke.
CGRA express: accelerating execution using dynamic operation fusion, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'09, ACM, 2009, pp. 271–280.
J. Rabaey.
Reconfigurable Processing: The Solution to Low-Power Programmable DSP, in: IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1997, vol. 1, pp. 275–278.
R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, A. Ivanov.
System-on-chip: reuse and integration, in: Proceedings of the IEEE, 2006, vol. 94, no 6, pp. 1050– 1069.
E. Salminen, A. Kulmala, T. D. Hamalainen.
Survey of Network-on-chip Proposals, in: White Paper, OCP-IP, 2008.
K. Seehyun, K. Kum, W. Sung.
Fixed-point optimization utility for C and C++ based digital signal processing programs, in: IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, nov 1998, vol. 45, no 11, pp. 1455 -1464.
G. Theodoridis, D. Soudris, S. Vassiliadis.
2, in: A survey of coarse-grain reconfigurable architectures and CAD tools, Springer Verlag, 2007.
Z. Ul-Abdin, B. Svensson.
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing, in: Microprocessors and Microsystems, 2009, vol. 33, no 3, pp. 161 - 178. [ DOI : 10.1016/j.micpro.2008.10.003 ]
G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm, J. Hammes.
Automatic compilation to a coarse-grained reconfigurable system-on-chip, in: ACM Trans. on Embedded Computing Systems, 2003, vol. 2, no 4, pp. 560–589.
C. Wolinski, M. Gokhale, K. McCave.
A polymorphous computing fabric, in: Micro, IEEE, 2002, vol. 22, no 5, pp. 56–68.
C. Wolinski, K. Kuchcinski, A. Postola.
UPaK: abstract unified pattern based synthesis kernel for hardware and software systems, in: University Booth, DATE 2007, Nice, France, May 2007.
Z. A. Ye, N. Shenoy, P. Baneijee.
A C compiler for a processor with a reconfigurable functional unit, in: Proc. ACM/SIGDA Int. Symp. on Field Programmable Gate-Arrays, FPGA, New York, NY, USA, ACM Press, 2000, pp. 95–100.