Project Team Cairn

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
PDF e-pub XML


Bibliography

Major publications by the team in recent years
[1]
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, no 3.
[2]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, no 1, p. 21-33.
[3]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[4]
S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, p. 10–18, Best Paper Award.
[5]
L. Imbert, A. Peirera, A. Tisserand.
A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, San Diego, California, U.S.A., F. T. Luk (editor), SPIE, August 2007, vol. 6697, no 66970N, p. 1–9.
http://dx.doi.org/10.1117/12.733652
[6]
K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, no 12-15.
[7]
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, p. 1–15.
[8]
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[9]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, p. 1-13, Article ID 562326, 13 pages.
[10]
C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, no 6.
[11]
A. Tisserand.
High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, no 1, p. 14–23, invited paper.
http://dx.doi.org/10.1504/IJHPSA.2007.013288
[12]
C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.
Publications of the year

Doctoral Dissertations and Habilitation Theses

[13]
S. Derrien.
Contributions à la conception d'architectures matérielles dédiées, University of Rennes 1, December 2011, Habilitation à Diriger des Recherches.
[14]
L. Devaux.
Réseaux d'interconnexion flexibles pour architectures reconfigurables dynamiquement, University of Rennes 1, November 2011.
[15]
D. Menard.
Contribution à la conception de systèmes en virgule fixe, University of Rennes 1, November 2011, Habilitation à Diriger des Recherches.
[16]
H.-N. Nguyen.
Optimisation de la précision de calcul pour la réduction d'énergie des systèmes embarqués, University of Rennes 1, December 2011.
[17]
E. Raffin.
Déploiement d'applications multimédia sur architecture reconfigurable à gros grain : modélisation avec la programmation par contraintes, University of Rennes 1, July 2011.
http://tel.archives-ouvertes.fr/docs/00/64/23/30/PDF/These_Erwan_Raffin.pdf

Articles in International Peer-Reviewed Journal

[18]
M. Alam, O. Berder, D. Menard, T. Anger, O. Sentieys.
A Hybrid Model for Accurate Energy Analysis of WSN nodes, in: EURASIP Journal on Embedded Systems, January 2011, vol. 2011, no Article ID 307079, p. 4:1–4:16.
http://dx.doi.org/10.1155/2011/307079
[19]
D. Blouin, D. Chillet, E. Senn, S. Bilavarn, R. Bonamy, C. Samoyeau.
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC, in: International Journal of Reconfigurable Computing, 2011, vol. 2011, no Article ID 425401, 15 p.
http://dx.doi.org/10.1155/2011/425401
[20]
G. Caffarena, O. Sentieys, D. Menard, J. A. López, D. Novo.
Editorial: Quantization of VLSI Digital Signal Processing Systems, in: EURASIP Journal on Advances in Signal Processing, 2011, vol. 2011, 2 p.
[21]
G. Caffarena, O. Sentieys, D. Menard, J. A. López, D. Novo.
Editors of the Special Issue on Quantization of VLSI Digital Signal Processing Systems, in: EURASIP Journal on Advances in Signal Processing, 2011, vol. 2011.
[22]
E. Casseau, B. Le Gal.
Design of multi-mode application-specific cores based on high-level synthesis, in: Integration, the VLSI Journal, January 2012, vol. 45, no 1, p. 9-21. [ DOI : 10.1016/j.vlsi.2011.07.003 ]
http://hal.inria.fr/hal-00631007/en
[23]
D. Chillet, A. Eiche, S. Pillement, O. Sentieys.
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network, in: Journal of Systems Architecture - Embedded Systems Design, April 2011, vol. 57, no 4, p. 340-353.
http://dx.doi.org/10.1016/j.sysarc.2011.01.004
[24]
B. Le Gal, E. Casseau.
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design, in: EURASIP Journal on Advances in Signal Processing, January 2011, vol. 2011, 11 p. [ DOI : 10.1155/2011/927670 ]
http://hal.inria.fr/hal-00631012/en
[25]
B. Le Gal, E. Casseau.
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis, in: Journal of Signal Processing Systems, March 2011, vol. 62, p. 341–357. [ DOI : 10.1007/s11265-010-0467-8 ]
http://hal.archives-ouvertes.fr/hal-00554228/fr/
[26]
Q.-T. Ngo, O. Berder, P. Scalart.
Minimum Euclidean distance based precoders for MIMO systems using rectangular QAM modulations, in: IEEE Transactions on Signal Processing, March 2011.
http://dx.doi.org/10.1109/TSP.2011.2177972
[27]
T.-D. Nguyen, O. Berder, O. Sentieys.
Energy-Efficient Cooperative Techniques for Infrastructure-to-Vehicle Communications, in: IEEE Transactions on Intelligent Transportation Systems, September 2011, vol. 12, no 3, p. 659 -668.
http://dx.doi.org/10.1109/TITS.2011.2118754
[28]
A. Pasha, S. Derrien, O. Sentieys.
System Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow, in: ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011.
[29]
E. Raffin, C. Wolinski, F. Charot, K. Kuchcinski, S. Guyetant, S. Chevobbe, E. Casseau.
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture, in: International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2011.
[30]
V. D. Tovinakere, O. Sentieys, S. Derrien.
A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters, in: Journal of Low Power Electronics (JOLPE), December 2011, vol. 7, no 4, p. 482-489.
[31]
R. Zhang, J.-M. Gorce, O. Berder, O. Sentieys.
Lower Bound of Energy-Latency Trade-off of Opportunistic Routing in Multi-hop Networks, in: EURASIP Journal on Wireless Communications and Networking, 2011, vol. 2011, no Article ID 265083, 17 p.
http://www.hindawi.com/journals/wcn/2011/265083.html

Articles in National Peer-Reviewed Journal

[32]
D. Pamula, E. Hrynkiewicz, A. Tisserand.
Analiza algorytmow mnozenia w ciele GF(2 m ), in: Pomiary, Automatyka, Kontrola (PAK), 2011, vol. 57, no 1, p. 58–60.
[33]
M. Pham, S. Pillement.
Reconfigurable ECU communications in AUTOSAR Environment, in: Ingénieurs de l'Automobile, 2011, vol. 813.

International Conferences with Proceedings

[34]
D. Adrouche, R. Sadoun, S. Pillement.
A design methodology for specification and performances evaluation of Network On Chip, in: Proc. IEEE International Workshop on Reliability Aware System Design and Test, Chennai, India, January 2011, p. 65–70.
[35]
M. Alam, O. Berder, D. Menard, O. Sentieys.
Accurate Energy Consumption Evaluation of Preamble Sampling MAC Protocols for WSN, in: Proc. of the Workshop on Ultra-Low Power Sensor Networks (WUPS), co-located with Int. Conf. on Architecture of Computing Systems (ARCS), Como, Italy, February 2011.
[36]
M. Alam, O. Berder, D. Menard, O. Sentieys.
Traffic-Aware Adaptive Wake-Up-Interval for Preamble Sampling MAC Protocols of WSN, in: Proc. of the International Workshop on Cross-Layer Design (IWCLD), Rennes, France, December 2011.
[37]
M. M. Azeem, Stanislaw J. Piestrak, O. Sentieys, S. Pillement.
Error recovery technique for coarse-grained reconfigurable architectures, in: Proc. IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), April 2011, p. 441-446.
http://dx.doi.org/10.1109/DDECS.2011.5783133
[38]
A. Banciu, E. Casseau, D. Menard, T. Michel.
Stochastic modeling for floating-point to fixed-point conversion, in: Proc. 2011 IEEE Workshop on Signal Processing Systems (SiPS), oct. 2011, p. 180 -185.
http://dx.doi.org/10.1109/SiPS.2011.6088971
[39]
V. Basupalli, T. Yuki, S. V. Rajopadhye, A. Morvan, S. Derrien, P. Quinton, D. Wonnacott.
ompVerify: Polyhedral Analysis for the OpenMP Programmer, in: 7th International Workshop on OpenMP, IWOMP, 2011, p. 37-53.
[40]
D. Blouin, E. Senn, R. Bonamy, D. Chillet, S. Bilavarn, C. Samoyeau.
FPGA Modeling for SoC Design Exploration, in: International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Londres, May 2011.
[41]
R. Bonamy, D. Chillet, S. Bilavarn, O. Sentieys.
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices, in: International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Londres, May 2011.
[42]
R. Bonamy, D. Chillet, S. Bilavarn, O. Sentieys.
Towards a power and energy efficient use of partial dynamic reconfiguration, in: Proc. 6th Int. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Montpellier, France, June 2011, p. 1–4.
http://dx.doi.org/10.1109/ReCoSoC.2011.5981540
[43]
A. Cornu, S. Derrien, D. Lavenier.
HLS Tools for FPGA : faster development with better performances, in: Proceeding of the 7th International Symposium on Applied Reconfigurable Computing, Belfast, United Kingdom, March 2011, vol. 6578, p. 67-78.
http://hal.inria.fr/hal-00637830/en
[44]
A. Eiche, D. Chillet, S. Pillement, O. Sentieys.
Parallel Evaluation of Hopfield Neural Networks, in: International Conference on Neural Computation Theory and Applications (NCTA), Paris, France, October 2011.
[45]
A. Floch, T. Yuki, C. Guy, S. Derrien, B. Combemale, S. Rajopadhye, R. B. France.
Model-Driven Engineering and Optimizing Compilers: A bridge too far ?, in: ACM/IEEE 14th International Conference on Model Driven Engineering Languages and Systems (Models'11), October 2011, p. 608-622.
http://hal.inria.fr/inria-00613575/en
[46]
M. Hamilton, W. P. Marnane, A. Tisserand.
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values, in: Proc. 21st International Conference on Field Programmable Logic and Applications (FPL), Chania, Greece, IEEE, September 2011, p. 273-276.
http://dx.doi.org/10.1109/FPL.2011.55
[47]
D. Menard, H.-N. Nguyen, F. Charot, S. Guyetant, J. Guillot, E. Raffin, E. Casseau.
Exploiting reconfigurable SWP operators for multimedia applications, in: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Prague, may 2011, p. 1717 -1720. [ DOI : 10.1109/ICASSP.2011.5946832 ]
http://hal.inria.fr/inria-00567017/en
[48]
A. Morvan, S. Derrien, P. Quinton.
Efficient Nested Loop Pipelining in High Level Synthesis using Polyhedral Bubble Insertion, in: IEEE International Conference on Field-Programmable Technology (FPT'11), New Delhi, India, December 2011, p. 1-10.
[49]
S. Narayanan, D. Chillet, S. Pillement, I. Sourdis.
Hardware OS Communication Service and Dynamic Memory Management for RSoCs, in: Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, November 2011.
[50]
S. Narayanan, L. Devaux, D. Chillet, S. Pillement, I. Sourdis.
Communication service for hardware tasks executed on dynamic and partially reconfigurable substrate, in: Proc. 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Hong-Kong, September 2011.
[51]
J.-C. Naud, Q. Meunier, D. Menard, O. Sentieys.
Fixed-point Accuracy Evaluation in the Context of Conditional Structures, in: Proc. 19th European Signal Processing Conference (EUSIPCO), Barcelona, Spain, September 2011.
[52]
Q.-T. Ngo, O. Berder, P. Scalart.
Neighbor-dmin Precoder for Three Data-Stream MIMO Systems, in: 19th European Signal Processing Conference (EUSIPCO), Barcelona, Spain, August 2011, p. 81-85.
[53]
Q.-T. Ngo, O. Berder, P. Scalart.
Reducing the number of neighbors in the received constellation of dmin precoded MIMO systems, in: Proc. of the IEEE Conference on Wireless Communications and Networking Conference (WCNC), Cancun, Mexico, March 2011, p. 1635 -1639.
http://dx.doi.org/10.1109/WCNC.2011.5779380
[54]
H.-N. Nguyen, D. Menard, O. Sentieys.
Novel Algorithms for Word-length Optimization, in: Proc. 19th European Signal Processing Conference (EUSIPCO), Barcelona, Spain, September 2011.
http://hal.inria.fr/inria-00617718/en
[55]
P. Patronik, K. Berezowski, S. J. Piestrak, J. Biernat, A. Shrivastava.
Fast and energy-efficient constant-coefficient FIR filters using residue number system, in: Proc. of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'11), 1-3 Aug. 2011, p. 385-390.
http://dx.doi.org/10.1109/ISLPED.2011.5993671
[56]
M. Pham, R. Bonamy, S. Pillement, D. Chillet.
Power-Aware Ultra-Rapid Reconfiguration Controller, in: Proc. IEEE/ACM Design and Test in Europe Conference (DATE), 2012.
[57]
M. Pham, L. Devaux, S. Pillement.
Re2DA: Reliable and Reconfigurable Dynamic Architectures, in: Proc. 6th Int. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), June 2011, p. 1–6.
http://dx.doi.org/10.1109/ReCoSoC.2011.5981519
[58]
M. Pham, S. Pillement, S. Le Nours, O. Pasquier.
A Framework for the Design of Reconfigurable Fault Tolerant Architectures, in: Proc. Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere Finland, November 2011.
[59]
S. J. Piestrak.
Design of multi-residue generators using shared logic, in: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 15-18 May 2011, p. 1435-1438.
http://dx.doi.org/10.1109/ISCAS.2011.5937843
[60]
P. Scalart, L. Lepauloux.
Highlighting the influence of artifacts signals on the equilibrium state of the feedback structure, in: Proc. 19th European Signal Processing Conference (EUSIPCO), Barcelona, Spain, September 2011.
http://hal.inria.fr/inria-00636259/en
[61]
M. Texier, R. David, K. B. Chehida, O. Sentieys.
Graphic rendering Application Profiling on a Shared Memory MPSoC Architecture, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere Finland, November 2011.
[62]
M. Texier, E. Piriou, M. Thevenin, R. David.
Designing Processors Using MAsS, a Modular and Lightweight Instruction-level Exploration Tool, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere Finland, November 2011.
[63]
V. D. Tovinakere, O. Sentieys, S. Derrien.
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters, in: Proc. of the 24th International Conference on VLSI Design, Chennai, India, January 2011, p. 340 - 345.
http://dx.doi.org/10.1109/VLSID.2011.18
[64]
L.-Q.-V. Tran, O. Berder, O. Sentieys.
Non-Regenerative Full Distributed Space-Time Codes in Cooperative Relaying Networks, in: Proc. of the IEEE International Wireless Communications and Networking Conference (WCNC), Cancun, Mexico, March 2011, p. 1529 - 1533.
http://dx.doi.org/10.1109/WCNC.2011.5779357
[65]
L.-Q.-V. Tran, O. Berder, O. Sentieys.
Spectral efficiency and energy efficiency of distributed space-time relaying models, in: Proc. of the IEEE Conference on Consumer Communications and Networking Conference (CCNC), Las Vegas, US, January 2011, p. 1088 -1092.
http://dx.doi.org/10.1109/CCNC.2011.5766335
[66]
C. Xiao, E. Casseau.
An efficient algorithm for custom instruction enumeration, in: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, New York, NY, USA, GLSVLSI '11, ACM, 2011, p. 187–192.
http://doi.acm.org/10.1145/1973009.1973047
[67]
C. Xiao, E. Casseau.
Efficient custom instruction enumeration for extensible processors, in: Proc. 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), sept. 2011, p. 211 -214.
http://dx.doi.org/10.1109/ASAP.2011.6043270
[68]
C. Xiao, E. Casseau.
Efficient Maximal Convex Custom Instruction Enumeration for Extensible Processors, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere Finland, November 2011.
[69]
H. Yviquel, E. Casseau, M. Wipliez, M. Raulet.
Efficient multicore scheduling of dataflow process networks, in: Proc. 2011 IEEE Workshop on Signal Processing Systems (SiPS), oct. 2011, p. 198 -203.
http://dx.doi.org/10.1109/SiPS.2011.6088974

National Conferences with Proceeding

[70]
D. Chillet, A. Eiche, S. Pillement, O. Sentieys.
Exploitation du concept de tolérance aux fautes des réseaux de neurones pour la résolution de problèmes d'optimisation, in: XXIIIe Colloque GRETSI - Traitement du Signal et des Images, Bordeaux, France, September 2011.
[71]
A. Floch, F. Charot, S. Derrien, K. Martin, A. Morvan, C. Wolinski.
Sélection d'instructions et ordonnancement parallèle simultanés pour la conception de processeurs spécialisés, in: Symposium en Architecture de Machines (Sympa'14), St Malo, France, May 2011.
http://hal.inria.fr/hal-00640999/en/
[72]
C. Guy, S. Derrien, B. Combemale, J.-M. Jezequel.
Vers un rapprochement de l'IDM et de la compilation, in: Journées sur l'Ingénierie Dirigée par les Modèles, Lille, France, June 2011.
http://hal.inria.fr/inria-00601670/en
[73]
J.-C. Naud, D. Menard, Q. Meunier, O. Sentieys.
Evaluation de la précision en virgule fixe dans le cas des structures conditionnelles, in: Symposium en Architecture de Machines (Sympa'14), Saint Malo, France, May 2011.
http://hal.inria.fr/inria-00617720/en
[74]
Q.-T. Ngo, O. Berder, P. Scalart.
Influence du nombre de symboles voisins sur les performances des systèmes MIMO précodés par le critère de la distance minimale, in: XXIIIe Colloque GRETSI - Traitement du Signal et des Images, Bordeaux, France, September 2011.
[75]
K. Parashar, O. Sentieys, D. Menard.
Approche hiérarchique pour l'optimisation de la précision des systèmes de traitement du signal utilisant l'arithmétique virgule fixe, in: XXIIIe Colloque GRETSI - Traitement du Signal et des Images, Bordeaux, France, September 2011.
[76]
A. Pasturel, A. Eiche, D. Chillet, S. Pillement, O. Sentieys.
Implémentation matérielle d'un réseau de neurones pour l'ordonnancement de tâches sur architectures multi-processeur hétérogènes, in: Symposium en Architecture de Machines (Sympa'14), Saint-Malo, France, May 2011.
[77]
M. Pham, S. Pillement, S. Le Nours, O. Pasquier.
Modélisation et implémentation de calculateurs reconfigurables tolérants aux fautes et communications flexibles intra-véhicules, in: Symposium en Architecture de Machines (Sympa'14), Saint-Malo, France, May 2011, p. 23–32.
[78]
L.-Q.-V. Tran, O. Berder, O. Sentieys.
Efficacités spectrale et énergétique des systèmes de relais, in: XXIIIe Colloque GRETSI - Traitement du Signal et des Images, Bordeaux, France, September 2011.

Conferences without Proceedings

[79]
D. Chillet.
JSimRisc : un outil pédagogique pour appréhender le fonctionnement pipeline et quelques techniques avancées mises en œuvre dans les processeurs récents, in: Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes (CETSIS), Trois Rivières, Québec, October 2011.

Scientific Books (or Scientific Book chapters)

[80]
F. Nouvel, P. Tanguy, S. Pillement, M. Pham.
Experiments of in-vehicle power line Communications, in: Vehicular Technologies, M. Almeida (editor), Intech, 2011, p. 255–278.

Scientific Popularization

[81]
A. Tisserand.
Comment produire des nombres vraiment aléatoires ?, October 2011, Exposé, Fête de la Science, Lannion.

Other Publications

[82]
R. Bonamy, D. Chillet, S. Bilavarn, O. Sentieys.
Towards a Power and energy Efficient Use of Partial Dynamic Reconfiguration, in: GDR SoC-SiP, Lyon, France, June 2011.
[83]
T. Chabrier, D. Pamula, A. Tisserand.
Hardware Random Recoding: Redundant Representations of Numbers, Side Channel Analysis, Elliptic Curve Cryptography, April 2011, Journées Codage et Cryptographie du GDR IM.
[84]
A. Cornu, S. Derrien, D. Lavenier.
How to accelerate genomic sequence alignment 4X using half an FPGA, July 2011.
http://www.eetimes.com/design/programmable-logic/4217568/How-to-accelerate-genomic-sequence-alignment-4X-using-half-an-FPGA?Ecosystem=programmable-logic
[85]
F. Nouvel, P. Tanguy, S. Le Nours, S. Pillement.
Architecture embarquée reconfigurable pour les communications intra-véhicule, 2011, Séminaire du GDR SoC-SiP.
[86]
O. Sentieys.
System-Level Synthesis of Ultra Low-Power WSN Node Controllers, May 2011, Séminaire du GDR SoC-SiP.
[87]
A. Tisserand.
Circuits for True Random Number Generation with On-Line Quality Monitoring, May 2011, Claude Shannon Institut Workshop on Coding and Cryptography.
[88]
A. Tisserand.
Opérateurs arithmétiques matériels, June 2011, Cours École Thématique ARCHI 2011.
http://archi11.univ-perp.fr/
References in notes
[89]
A. Ahmadinia, C. Bobda, M. Bednara, J. Teich.
A new approach for on-line placement on reconfigurable devices, in: 18th International Parallel and Distributed Processing Symposium, 2004., 2004.
[90]
Z. Alliance.
Zigbee specification, ZigBee Alliance, 2005, no ZigBee Document 053474r06, Version.
[91]
V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.
PACT XPP — A Self-Reconfigurable Data Processing Architecture, in: The Journal of Supercomputing, 2003, vol. 26, no 2, p. 167–184.
[92]
C. Bobda.
Introduction to Reconfigurable Computing: Architectures Algorithms and Applications, Springer, 2007.
[93]
C. Bobda, M. Majer, D. Koch, A. Ahmadinia, J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices, in: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, Lecture Notes in Computer Science (LNCS), Springer, August 2004, vol. 3203, p. 1032–1036.
[94]
D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.
[95]
K. Compton, S. Hauck.
Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, no 2, p. 171–210.
http://doi.acm.org/10.1145/508352.508353
[96]
G. Constantinides, P. Cheung, W. Luk.
Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, no 10, p. 1432- 1442.
[97]
K. Danne, R. Muhlenbernd, M. Platzner.
Executing hardware tasks on dynamically reconfigurable devices under real-time conditions, in: International Conference on Field Programmable Logic and Applications, Lecture Notes in Computer Science, 2006.
[98]
R. David, S. Pillement, O. Sentieys.
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