Inria / Raweb 2010
Presentation of the Project Cairn

Bibliography

Major publications by the team in recent years

[1]: L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, n^o 3.
[2]: A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, n^o 1, p. 21-33.
[3]: R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[4]: S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, p. 10–18, Best Paper Award.
[5]: L. Imbert, A. Peirera, A. Tisserand.
A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, San Diego, California, U.S.A., F. T. Luk (editor), SPIE, August 2007, vol. 6697, n^o 66970N, p. 1–9.
http://dx.doi.org/10.1117/12.733652
[6]: K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, n^o 12-15.
[7]: D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, n^o 1, p. 1–15.
[8]: D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[9]: S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, p. 1-13, Article ID 562326, 13 pages.
[10]: C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, n^o 6.
[11]: A. Tisserand.
High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, n^o 1, p. 14–23, invited paper.
http://dx.doi.org/10.1504/IJHPSA.2007.013288
[12]: C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, n^o 4-6.

Publications of the year

Doctoral Dissertations and Habilitation Theses

[13]: D. Chillet.
Contribution à la gestion dynamique de ressources reconfigurables intégrées au sein d'un MPSoC, University of Rennes 1, June 2010.
[14]: E. Grace.
Hiérarchie mémoire reconfigurable faible consommation pour systèmes enfouis, University of Rennes 1 - ENSSAT, October 2010.
[15]: S. Khan.
Development of high performance hardware architectures for multimedia applications, University of Rennes 1 - ENSSAT, September 2010.
[16]: K. Martin.
Génération automatique d'extensions de jeux d'instructions de processeurs, University of Rennes 1, September 2010.
http://tel.archives-ouvertes.fr/tel-00526133/PDF/these_KevinMartin.pdf
[17]: A. Pasha.
System-Level Synthesis of Ultra Low-Power Wireless Sensor Network Node Controllers: A Complete Design-Flow, University of Rennes 1 - ENSSAT, December 2010.
[18]: H. M. Pham.
Apport de la reconfiguration dynamique dans les architectures tolérantes aux fautes, University of Rennes 1 - ENSSAT, December 2010.
[19]: S. Pillement.
Calcul reconfigurable dynamiquement : du transistor à l'application, University of Rennes 1, October 2010.
[20]: A. Tisserand.
Étude et conception d'opérateurs arithmétiques, University of Rennes 1, July 2010.

Articles in International Peer-Reviewed Journal

[21]: M. Alam, O. Berder, D. Menard, T. Anger, O. Sentieys.
A Hybrid Model for Accurate Energy Analysis of WSN nodes, in: EURASIP Journal on Embedded Systems, 2011, to appear.
[22]: C. Andriamisaina, P. Coussy, E. Casseau, C. Chavet.
High-Level Synthesis for Designing Multimode Architectures, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 2010, vol. 29, n^o 11, p. 1736 -1749.
http://dx.doi.org/10.1109/TCAD.2010.2062751
[23]: D. Chillet, S. Pillement, O. Sentieys.
Real-Time Scheduling on Heterogeneous SoC Architectures Using Inhibitor Neurons in a Neural Network, in: Journal of Systems Architecture, 2011, to appear.
[24]: A. Courtay, J. Laurent, O. Sentieys.
Spatial Switching data coding technique analysis and improvements for interconnect power consumption optimization, in: Journal of Low Power Electronics (JOLPE), April 2010, vol. 6, n^o 1, p. 32-43.
[25]: S. Derrien, P. Quinton.
Hardware Acceleration of HMMER on FPGAs, in: Journal of Signal Processing Systems, October 2010, vol. 58, n^o 1, p. 53–67.
http://dx.doi.org/10.1007/s11265-008-0262-y
[26]: L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, D. Demigny.
Flexible interconnection network for dynamically and partially reconfigurable architectures, in: International Journal on Reconfigurable Computing (IJRC), 2010, vol. 2010, n^o article ID 390545, 15 pages p.
http://dx.doi.org/10.1155/2010/390545
[27]: S. Khan, E. Casseau, D. Menard.
High speed reconfigurable SWP operator for multimedia processing using redundant data representation, in: Int. Journal of Information Sciences and Computer Engineering (IJISCE), May 2010, vol. 1, p. 45-52.
http://hal.inria.fr/inria-00480330/en/
[28]: G. Le Jan, R. Le Bouquin-Jeannès, N. Costet, N. Trolès, P. Scalart, D. Pichancourt, G. Faucon, J.-E. Gombert.
Multivariate predictive model for dyslexia diagnosis, in: Annals of Dyslexia, 2010, p. 1-20.
http://dx.doi.org/10.1007/s11881-010-0038-5
[29]: B. Le Gal, E. Casseau.
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis, in: Journal of Signal Processing Systems, April 2010, vol. 2010, n^o Online, p. 1–17.
http://dx.doi.org/10.1007/s11265-010-0467-8
[30]: S. Piestrak, S. Pillement, O. Sentieys.
Comments on 'A low-power dependable Berger code for fully asymmetric communication', in: IEEE Communications Letters, August 2010, vol. 14, n^o 8, p. 761-763.
http://dx.doi.org/10.1109/LCOMM.2010.08.100447
[31]: S. Piestrak, S. Pillement, O. Sentieys.
On designing efficient codecs for bus-invert Berger code for fully asymmetric communication, in: IEEE Transactions on Circuits and Systems II, October 2010, vol. 57, n^o 10, p. 777 -781.
http://dx.doi.org/10.1109/TCSII.2010.2067773
[32]: S. Pillement, J. Philippe, O. Sentieys.
Spatio-temporal Coding to Improve Speed and Noise Tolerance of On-chip Interconnect, in: MicroElectronics Journal, 2010, vol. 41, n^o 8, p. 480 - 486. [ DOI : DOI: 10.1016/j.mejo.2009.11.001 ]
http://www.sciencedirect.com/science/article/B6V44-4Y0547M-1/2/4634f1a0a8cc2bd49ae33ceede13beb0
[33]: R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Accuracy Evaluation of Fixed-Point based LMS Algorithm, in: Digital Signal Processing, May 2010, vol. 20, n^o 3, p. 640-652. [ DOI : doi:10.1016/j.dsp.2009.10.007 ]
http://hal.inria.fr/inria-00450935/en/
[34]: R. Zhang, J. Gorce, O. Berder, O. Sentieys.
Lower Bound of Energy-Latency Trade-off of Opportunistic Routing in Multi-hop Networks, in: EURASIP Journal on Wireless Communciations and Networking, 2010, to appear.

Articles in National Peer-Reviewed Journal

[35]: L. Devaux, S. Pillement, D. Chillet, D. Demigny.
DRAFT : réseau flexible pour architecture reconfigurable dynamiquement, in: Technique et Science Informatiques (TSI), 2011, to appear.
http://hal.inria.fr/inria-00536704/en/

Invited Conferences

[36]: T. Chabrier, D. Pamula, A. Tisserand.
Hardware implementation of DBNS recoding for ECC processor, in: Proc. of the 44rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., IEEE, November 2010.

International Peer-Reviewed Conference/Proceedings

[37]: N. Abbas, S. Derrien, S. Rajopadhye, P. Quinton.
Accelerating HMMER on FPGA using Parallel Prefixes and Reductions, in: Proc. of the IEEE International Conference on Field-Programmable Technology (FPT'10), Beijing, China, December 2010, p. 37-44.
http://dx.doi.org/10.1109/FPT.2010.5681755
[38]: A. Banciu, E. Casseau, D. Menard, T. Michel.
A Case Study Of The Stochastic Modeling Approach For Range Estimation, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Edinburgh, UK, October 2010, p. 301–308.
[39]: C. Beaumin, O. Sentieys, E. Casseau, A. Carer.
A Coarse-Grain Reconfigurable Hardware Architecture for RVC-CAL-based Design, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Edinburgh, UK, October 2010, p. 161–168.
[40]: O. Berder, O. Sentieys.
PowWow: Power Optimized Hardware/Software Framework for Wireless Motes, in: Proc. of the Workshop on Ultra-Low Power Sensor Networks (WUPS), co-located with Int. Conf. on Architecture of Computing Systems (ARCS 2010), Hannover, Germany, February 2010, p. 229–233.
[41]: F. Berthelot, F. Charot, C. Wagner, C. Wolinski.
Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation, in: Proc. of the 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2010), Lille France, September 2010, p. 667 - 674.
http://hal.inria.fr/inria-00480723/en/
[42]: L. Devaux, S. Pillement, D. Chillet, D. Demigny.
Mesh and Fat-Tree comparison for dynamically reconfigurable applications, in: Proc. of the Reconfigurable Communication-centric Systems on Chip (ReCoSoC'10), Karlsruhe, Germany, May 2010.
[43]: L. Devaux, S. Pillement, D. Chillet, D. Demigny.
Operating System Services for Reconfigurable System-on-Chip Communication, in: Proc. of the Design of Circuits and Intergrated Systems (DCIS'10), Canary Islands, Spain, November 2010.
http://hal.inria.fr/inria-00536709
[44]: L. Devaux, S. Pillement, D. Chillet, D. Demigny.
R2NoC: dynamically Reconfigurable Routers for flexible Networks on Chip, in: Proc. of the International Conference on ReConFigurable Computing and FPGAs (ReConFig'10), Cancun, Mexico, December 2010.
http://hal.inria.fr/inria-00536711
[45]: A. Eiche, D. Chillet, S. Pillement, O. Sentieys.
Task placement for dynamic and partial reconfigurable region, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Edinburgh, UK, October 2010, p. 82-88.
http://hal.inria.fr/inria-00536714
[46]: A. Floch, C. Wolinski, K. Kuchcinski.
Combined Scheduling and Instruction Selection for Processors with Reconfigurable Cell Fabric, in: 21th IEEE International Conference on Application-specific Systems, Architectures and Processors, (ASAP 2010), Rennes France, IEEE, July 2010.
http://hal.inria.fr/inria-00480680/en/
[47]: J. Frigo, E. Raby, S. Brennan, C. Wolinski, C. Wagner, F. Charot, E. Rosten, V. Kulathumani.
Energy efficient sensor node implementations, in: Proc. of the 18th annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'10), New York, NY, USA, ACM, 2010, p. 37–40. [ DOI : 10.1145/1723112.1723120 ]
http://hal.inria.fr/inria-00451689/fr
[48]: T. M. N. Hoang, S. Ragot, B. Kövesi, P. Scalart.
Parametric stereo extension of ITU-T G.722 based on a new downmixing scheme, in: Proc. of the IEEE Multimedia Signal Processing Conference, Saint-Malo France, October 2010, p. 188 - 193. [ DOI : 10.1109/MMSP.2010.5662017 ]
http://hal.inria.fr/inria-00512646/en/
[49]: S. M. A. H. Jafri, S. Piestrak, O. Sentieys, S. Pillement.
Design of a fault-tolerant coarse-grained reconfigurable architecture: A case study, in: Proc. of the 11th IEEE International Symposium on Quality Electronic Design (ISQED 2010), San Diego, CA, USA, IEEE, March 2010, 6 pages p.
[50]: L. Lepauloux, P. Scalart, C. Marro.
Computationally efficient and robust frequency-domain GSC, in: Proc. of the 12th IEEE International Workshop on Acoustic Echo and Noise Control, Tel-Aviv Israel, August 2010, p. 1-4.
http://hal.archives-ouvertes.fr/inria-00512654/en/
[51]: D. Menard, D. Novo, R. Rocher, F. Catthoor, O. Sentieys.
Quantization Mode Opportunities in Fixed-Point System Design, in: Proc. of the XVIII European Signal and Image Processing Conference (EUSIPCO'10), Aalborg, Denmark, EURASIP, August 2010, p. 542-546.
http://hal.inria.fr/inria-00534526/en/
[52]: Q.-T. Ngo, O. Berder, P. Scalart.
3-D minimum Euclidean distance based sub-optimal precoder for MIMO spatial multiplexing systems, in: Proc. of the IEEE International Conference on Communications (ICC), Cape Town, South Africa, June 2010, p. 1-5.
http://dx.doi.org/10.1109/ICC.2010.5502075
[53]: T. Nguyen, O. Berder, O. Sentieys.
Cooperative MISO and Relay Comparison in Energy Constrained WSNs, in: Proc. of the 71st IEEE International Vehicular Technology conference (VTC), Taipei, Taiwan, May 2010, p. 1-5.
http://dx.doi.org/10.1109/VETECS.2010.5493688
[54]: T. Nguyen, L. Mai, O. Berder, O. Sentieys.
Cooperative MIMO and Relay Association Strategy, in: International Conferences on Advanced Technologies for Communications (ATC), Ho Chi Minh city, Vietnam, October 2010, p. 327 - 330.
http://dx.doi.org/10.1109/ATC.2010.5672699
[55]: D. Pamula, E. Hrynkiewicz, A. Tisserand.
Multiplication in GF(2^m ): area and time dependency/efficiency/complexity analysis, in: Proc. of the 10th International IFAC Workshop on Programmable Devices and Embedded Systems (PDeS), Pszczyna, Poland, IFAC, October 2010.
[56]: K. Parashar, R. Rocher, D. Menard, O. Sentieys, D. Novo, F. Catthoor.
Fast performance evaluation of fixed-point systems with un-smooth operators, in: Proc. of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD, San Jose, CA, IEEE/ACM, November 2010, p. 9-16.
http://hal.inria.fr/inria-00534527/en/
[57]: K. Parashar, R. Rocher, D. Menard, O. Sentieys.
A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems, in: Proc. of the 23rd International Conference on VLSI Design, VLSID'10, Bangalore, India, January 2010, p. 318–323. [ DOI : 10.1109/VLSI.Design.2010.66 ]
http://hal.inria.fr/inria-00432590/en/
[58]: K. Parashar, R. Rocher, D. Menard, O. Sentieys.
Analytical Approach for Analyzing Quantization Noise Effects on Decision Operators, in: Proc. of the 35th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Dallas, Texas, USA, March 2010, p. 1554 - 1557. [ DOI : 10.1109/ICASSP.2010.5495520 ]
http://hal.inria.fr/inria-00534522/en/
[59]: K. Parashar, R. Rocher, D. Menard, O. Sentieys.
Estimating Frequency Characteristics of Quantization Noise for Performance Evaluation of Fixed Point Systems, in: Proc. of the XVIII European Signal and Image Processing Conference (EUSIPCO'10), Aalborg, Denmark, EURASIP, August 2010, p. 552-556.
http://hal.inria.fr/inria-00534524/en/
[60]: K. Parashar, D. Menard, R. Rocher, O. Sentieys.
Shaping Probability Density Function of Quantization Noise in Fixed Point Systems, in: Proc. of the 44th Annual Asilomar Conference on Signals, Systems, and Computers, Monterey, CA, November 2010.
http://hal.inria.fr/inria-00534529/en/
[61]: A. Pasha, S. Derrien, O. Sentieys.
A Complete Design-Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-Tasking, in: Proc. of the 47th IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, USA, June 2010, p. 693 - 698.
[62]: A. Pasha, S. Derrien, O. Sentieys.
A Novel Approach for Ultra Low-Power WSN Node Generation, in: Proc. of the IET Irish Signals and Systems Conference (ISSC 2010), Cork, Ireland, June 2010, p. 204 - 209.
http://dx.doi.org/10.1049/cp.2010.0513
[63]: A. Pasha, S. Derrien, O. Sentieys.
System-Level Synthesis for Ultra Low-Power Wireless Sensor Nodes, in: Proc. of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Lille, France, September 2010, p. 493 - 500.
http://dx.doi.org/10.1109/DSD.2010.88
[64]: M. Pham, L. Devaux, S. Pillement.
Dynamic NOC-based MPSoC with Fault-Tolerance Support, in: DAC Workshop on "Diagnostic Services in Network-on-Chips (DSNoC)", Anaheim, USA, june 2010.
[65]: M. Pham, S. Pillement, D. Demigny.
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC, in: Proc. of the 2010 International Conference on Field Programmable Logic and Applications (FPL), Milano, Italy, October 2010, p. 159-162.
http://hal.inria.fr/inria-00536720
[66]: M. Pham, S. Pillement, D. Demigny.
FT-DyMPSoC: Analytical Model for Fault-Tolerant Dynamic MPSoC, in: Proc. of the 18th Int. IEEE Symposium on Field-Programmable Custom Computing Machines, Charlotte, North Carolina, may 2010, poster.
[67]: S. Piestrak.
Design of cost-efficient multipliers modulo 2^a-1 , in: Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, June 2010, p. 4093 - 4096.
http://dx.doi.org/10.1109/ISCAS.2010.5537626
[68]: S. Piestrak.
On reducing error rate of data protected using systematic unordered codes in asymmetric channels, in: Proc. of the 13th Euromicro Conference on Digital System Design (DSD 2010), Lille, France, September 2010, p. 133-140.
http://dx.doi.org/10.1109/DSD.2010.117
[69]: E. Raffin, C. Wolinski, F. Charot, K. Kuchcinski, S. Guyetant, S. Chevobbe, E. Casseau.
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Edinburgh, UK, October 2010, p. 12–19, Best Paper Award.
http://hal.inria.fr/inria-00539874/PDF/dasip2010.pdf
[70]: P. Scalart, L. Lepauloux.
On the convergence behavior of recursive adaptive noise cancellation structure in the presence of crosstalk, in: Proc. of the IEEE International Conference on Sensor Signal Processing for Defence (SSPD), London, UK, 2010.
[71]: M. Thériault, S. Roy, O. Sentieys.
Transmitter Architecture for the Evaluation of Beamforming Schemes in the IEEE 802.11n Standard, in: Proc. of the 11th annual IEEE Wireless and Microwave Technology (WAMI) Conference, Melbourne, FL, USA, April 2010, p. 1-4.
http://dx.doi.org/10.1109/WAMICON.2010.5461867
[72]: A. Tisserand.
Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC, in: Proc. of the 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Lyon, France, September 2010.
[73]: L. Tran, O. Berder, O. Sentieys.
Energy Efficiency of Cooperative Strategies in Wireless Sensor Networks, in: International Conferences on Advanced Technologies for Communications (ATC), Ho Chi Minh city, Vietnam, October 2010, p. 29 - 32.
http://dx.doi.org/10.1109/ATC.2010.5672727
[74]: T.D. Vivek, O. Sentieys, S. Derrien.
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters, in: Proc. of the 24th International Conference on VLSI Design, Chennai, India, January 2011.
[75]: C. Wolinski, K. Kuchcinski, K. Martin, A. Floch, E. Raffin, F. Charot.
Graph Constraints in Embedded System Design, in: Worshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Bologne Italie, June 2010.
http://hal.inria.fr/inria-00481135/en/

Workshops without Proceedings

[76]: A. Tisserand, T. Chabrier, D. Pamula.
Arithmetic Level Countermeasures for ECC Coprocessor, in: Workshop on Coding and Cryptography, May 2010, Claude Shannon Institut Workshop on Coding and Cryptography.
[77]: C. Xiao, E. Casseau.
Pattern Extraction for Digital Design, in: National Workshop of the GdR SoC-SiP (System-On-Chip & System-In-Package), Paris, France, June 2010.

Scientific Books (or Scientific Book chapters)

[78]: D. Chillet, S. Pillement, O. Sentieys.
RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip, in: Algorithm-Architecture Matching for Signal and Image Processing, Springer, 2010, p. 117-144.
[79]: F. Nouvel, P. Tanguy, S. Pillement, M. Pham.
Experiments of in-vehicle power line Communications, in: Vehicular Technologies, Intech, 2011, 15 p, Accepted for publication.

Books or Proceedings Editing

[80]: F. Charot, F. Hannig, J. Teich, C. Wolinski (editors)
ASAP 2010: 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, Institute of Electrical and Electronics Engineers (IEEE, Rennes, France, July 2010.

Scientific Popularization

[81]: O. Sentieys, O. Berder.
Réseaux de capteurs sans fil, October 2010, Fête de la science.
[82]: A. Tisserand.
Puces électroniques et sécurité numérique, October 2010, Fête de la science.

References in notes

[83]: A. Ahmadinia, C. Bobda, M. Bednara, J. Teich.
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[86]: C. Bobda.
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A Dynamic NoC Approach for Communication in Reconfigurable Devices, in: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, Lecture Notes in Computer Science (LNCS), Springer, August 2004, vol. 3203, p. 1032–1036.
[88]: D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.
[89]: K. Compton, S. Hauck.
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Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, n^o 10, p. 1432- 1442.
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