Section: New Results
Energy-aware control for systems on-chip
The NeCS team is involved in the ARAVIS project (see 7.1 at http://www.minalogic.com/posters/aravis.pdf ) : the high level of integration in future chips will lead to heterogeneity in the performance of the various integrated components. It appears that introducing control loops at different levels of these chips will be necessary to be compliant with heterogeneous circuits.
Energy-Aware Control Design for Voltage Scaling Converters
Participants : C. Canudas-de-Wit [ contact person ] , C. Albea-Sanchez.
In low-power electronics, achieving high energy efficiency has great relevance. Global Asynchronous Local Synchronous Systems enables to use a Local Dynamic Voltage Scaling architecture, this technique allows to achieve a high energy efficiency. Moreover, Local Dynamic Voltage Scaling can be implemented using different approaches. One of them is Vdd-Hopping technique.
We have continued our researches in the context of the ARAVIS project. An energy-aware controller has been designed for a Vdd-Hopping system dealing with current peak constraints. It improves considerably the system efficiency (transistor losses during the switching phases) and achieves fast time responses. The stability of this controller has been studied in  . Further studies, concerning the control implementation and more specifically the control parameters tuning accounting for the delay associated to the critical gate transmission, have been performed.
This controller named (ENARC: Energy-Aware Control) has been patented  .
Energy aware computing power control
Participants : N. Marchand [ contact person ] , S. Durand.
Achieving a good tradeoff between computing power and energy consumption is one of the challenges in embedded architectures of the future. This management is especially difficult for 45nm or 32nm known to be at the limit of the scalability, i.e. with a high process variability. Automatic control loops have therefore to be designed in order to make the performance fit the requirement in order to minimize the energy loss in a context of highly unknown performance of the chip. The main objective is to dynamically control the computing power and the consumption using the voltage and the frequency according to the requirements of the OS. In this way, a robust control law was developed  in order to minimize the high voltage running time with predictive technique, i.e. to minimize the energy consumption. Results are shown on figure 11 where the robustness is illustrated for 10% and 20% of process variability.
This control was done for one node (i.e. a processor) but in ARAVIS SoC, the chip is composed of several clusters with several nodes each (see figure 12 ). Thus, the energy controller has to manage the voltage level (one voltage domain by cluster) and the frequency for all nodes: a maximal frequency is performed for critical node and then a ratio of this frequency could be apply to the other nodes. Thus, a multicore control strategy with low computational needs was proposed  .
Two patents have been deposed: the first one for the monocore energy control  and the second one for the multicore energy control  .
Participants : D. Simon [ Contact person ] , A.-M. Alt.
An application software deployment based on a static and worst case point of view is no longer effective for such heterogeneous chips and more flexible designs must be used. It appears that closed loop control can be integrated at several hardware and software levels of the chips to provide both adaptivity to the operation conditions and robustness w.r.t. variability.
On top of the clusters power control and computing speed control layers, the outer application layer will include a feedback controller for the application quality of service (QoS) under constraints of computing and energy resources availability. This loop uses the scheduling parameters provided by the operating system to control the application's QoS. In the context of Aravis the computing speed of each integrated node is a controllable scheduling parameter.
Current work is focusing on the analysis and control of a H264/SVC video decoder. First the possible sensors and control variable must be defined. The SVC (Scalable Video Coding) extension of the H264 protocol  provides several profiles to scale the video decoding quality. Experiments using the JSVM reference software of H264/SVC, running on Linux, has shown that the image resolution and quantization step have both an impact on the computing load and on the decoded image quality measured by the Peak Noise to Signal Ratio (PSNR) between the original and decoded images. Moreover the observed relationships between the used decoding parameters and computing load look like affine functions, so that simple control stategies are expected to provide effective results  .
As the Aravis chip will use clusters of computing nodes, a parallel version of the decoding algorithm is currently under development using the event-based programming model and associated tools provided by the Sardes team.