Section: New Results
SimSoC Full System Simulation
Participants : Vania Joloboff, Helmstetter Claude, Hui Xiao.
The SimSoC simulator software has been developed. The ARM simulator has been completed to include the MMU and simulate ARM 9 subsystem, including a simulation model for the PrimeCell interrupt controller.
A UART controller and a flash memory controller simulation model have been also been implemented simulating some flash memory models from ST Microelectronics. Gathering the simulation models for processor, interrupt controller and other peripherals, a full system simulator has been developed for a specific System On Chip from ST Microelectronics. Embedded Linux as distributed on ST web site for this SoC can now be run over that simulator  . In this simulator, the simulated UART is connected to a window of the Graphical User Interface so that users can login on Linux using the simulated serial line.
SimSoC network simulation and debug
Participants : Vania Joloboff, Hui Xiao, Seng Patrice, Combier Pascal, Yuning Pang.
An Ethernet controller simulator has been developed, allowing for the connection of two simulated systems running TCP/IP stack. A small network simulation layer was developed so that N simulated systems using the simulated Ethernet controller can connect together as if they were connected to the real network. It is therefore possible to have several simulated systems running on the same host machine or on multiple networked machines to communicate with Ethernet frames over a simulated network. In addition, this simulated network can be connected to the real world, for example to ping 'inria.fr' from a simulated system.
A framework was added to the simulator such that simulated programs can be debugged from any debugger compliant with the GDB protocol for remote debugging. This framework is mostly architecture independent, with only architecture dependent plug-ins. A complete implementation was developed for debugging ARM platforms.
PowerPC and MIPS simulation with debug
Participants : Vania Joloboff, Bin Liu, Ming Liu, Hui Xiao, Bing Zhou.
An experiment has started to explore parallell simulation in the case of multi-core System-On-Chips. The idea explored is to parallelize simulation of processors while maintaining a serialized simulation of devices in SystemC.
The simulation of PowerPC and MIPS architectures has started. A complete ISS in interpreted mode has been developed for PowerPC, including the Memory Management Unit (MMU). A subset of the dual core Freescale 82641D SoC has been simulated. This simulator can can run U-Boot and Embedded Linux with limited pheripheral devices.
ARMv6 instruction set formalization
Participants : Frédéric Blanqui, Jean-François Monin, Xiaomu Shi.
We recently started to work on the certification of our simulator SimSoC by formalizing in Coq the ARMv6 instruction set, its binary encoding/decoding, and its semantics, reusing Xavier Leroy's work on logical and arithmetic operations on 32-bits words for CompCert(http://compcert.inria.fr ) . We cannot reuse CompCert's simplified formalization of the ARM instruction set and semantics as it is, since we want to be able to simulate every detail of an ARM processor, including exceptions and other imperative mechanisms.