Section: New Results
A simulation infrastructure for CCSL, the timing model of UML MARTE
Participants : Huafeng Yu, Loïc Besnard, Thierry Gautier, Jean-Pierre Talpin.
In the framework of the CESAR project, our work concerns formal analysis and simulation for the design of embedded systems. We are interested in timed systems that can be specified by using clock constraint specification language (CCSL) [52] introduced in the MARTE profile [61] . These systems subject to clock constraints are modeled, specified, analyzed, and simulated within two software environments: TimeSquare [49] and Polychrony. Clock constraints are solved using a heuristic algorithm in TimeSquare, which is generally non-deterministic. Simulation can be carried out and demonstrated in the form of waves. In comparison, Polychrony enables deterministic specifications and formal analysis for the design of safety-critical systems. It is a promising approach to integrate the complementary technologies present in the two software environments for the purpose of system design.
In order to benefit from the advantages provided by Polychrony, the clock constraints specified in CCSL are translated into Signal, therefore, they are analyzed by tools and technologies associated with Polychrony. For instance, the hierarchization technique is used for the clock analysis and affine clock system allows clock synchronization analysis. In addition, the code generated in C or Java by Polychrony enables to obtain deterministic execution traces, compared to the traces obtained by the constraint solver of TimeSquare. Furthermore, some expected properties such as invariance and reachability can be specified so that a controller can be calculated and synthesized (through Sigali) to ensure these properties on target system. Hierarchization extension is also expected so that it can be applied directly on CCSL clock constraints without a Signal translation.
It is also interesting to translate clock relations specified in Signal into CCSL for the simulation purpose as TimeSquare provides a graphical interface for simulation demonstration as well as non-deterministic specifications can be handled. However only Boolean equations are considered in Signal due to CCSL expressivity. The first advantage of this approach is that non-deterministic simulation driven by the constraints solver in TimeSquare can be carried out even if the original Signal program is rejected by the Signal compiler due to the non-determinism issue. The second advantage is that graphical demonstrations of simulation results in the format of waveform are enabled for Polychrony.
