Inria / Raweb 2009
Presentation of the Project DaRT

Bibliography

Major publications by the team in recent years

[1]: A. C. Aljundi, J.-L. Dekeyser, M. T. Kechadi, I. D. Scherson.
A universal performance factor for multi-criteria evaluation of multistage interconnection networks, in: Future Generation Comp. Syst., 2006, vol. 22, n^o 7, p. 794-804.
[2]: P. Boulet, C. Dumoulin, A. Honoré.
Model Driven Engineering for System-on-Chip Design, in: From MDD concepts to experiments and illustrations, S. Gérard, J.-P. Babeau, J. Champeau (editors), ISTE, September 2006, n^o 6
http://iste.co.uk/index.php?f=a&ACTION=View&id=147, ISBN:1-905209-59-0.
[3]: A. Cuccuru, J.-L. Dekeyser, P. Marquet, P. Boulet.
Towards UML 2 extensions for compact modeling of regular complex topologies, in: MODELS/UML 2005, ACM/IEEE 8th international conference on model driven engineering languages and systems, Montego Bay, Jamaica, October 2005.
[4]: A. Gamatié, É. Rutten, H. Yu, P. Boulet, J.-L. Dekeyser.
Synchronous Modeling and Analysis of Data Intensive Applications, in: EURASIP Journal on Embedded Systems,eurasip, july 2008, vol. 2008, Article ID 561863.
[5]: C. Glitia, P. Dumont, P. Boulet.
Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing, in: Multidimensional Systems and Signal Processing, 2009
http://springerlink.com/content/w3821760381l4432/?p=fc0a4428f2f4468a9d630d2a434a6f69&pi=0.
[6]: J. Khan, S. Niar, A. Menhaj, Y. El-Hillali, J.-L. Dekeyser.
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system, in: Application-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on, July 2008, p. 126-131.
[7]: O. Labbani, J.-L. Dekeyser, É. Rutten.
Safe Design Methodology for an Intelligent Cruise Control System with GPS, in: VTC'2006 Fall: 64th IEEE Vehicular Technology Conference, Montréal, Québec, Canada, September 2006, (Also appeared as an IEEE ITSS Newsletter in December 2006).
[8]: S. Le Beux, P. Marquet, J.-L. Dekeyser.
A Model Driven Co-Design Approach for High Perforamnce Embedded Systems Dedicated to Transport, in: Studies in Informatics and Control Journal, 2008, vol. 2008, n^o 4.
[9]: P. Marquet, S. Duquennoy, S. Le Beux, S. Meftali, J.-L. Dekeyser.
Massively Parallel Processing on a Chip, in: ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
[10]: H. Sbeyti, S. Niar, L. Eeckhout.
Pattern-Driven Prefetching for Multimedia Applications on Embedded Processors, in: Journal of System Architecture, April 2006, vol. 52, n^o 4, p. 199-212.
[11]: J. Taillard, F. Guyomarc'h, J.-L. Dekeyser.
A Graphical Framework for High Performance Computing using an MDE Approach, in: 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Toulouse, France, February 2008.

Publications of the year

Doctoral Dissertations and Habilitation Theses

[12]: C. Glitia.
Optimisation des applications de traitement systématique intensives sur System-on-Chip, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, Lille, France, November 2009, in french.
[13]: J. Taillard.
Une approche orientée modèle pour la parallélisation d'un code de calcul éléments finis, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, Lille, France, February 2009, in french.

Articles in International Peer-Reviewed Journal

[14]: C. Brunette, J.-P. Talpin, A. Gamatié, T. Gautier.
A Metamodel for the Design of Polychronous Systems, in: Journal of Logic and Algebraic Programming - JLAP, Special Issue on Applying Concurrency Research to Industry, January 2009.
[15]: R. Gaignaire, F. Guyomarc'h, O. Moreau, S. Clenet, B. Sudret.
Speeding Up SSFEM Computation Using Kronecker Tensor Products, in: IEEE TRANSACTIONS ON MAGNETICS, March 2009, vol. 45, n^o 3, p. 1432–1435.
[16]: A. Gamatié, É. Rutten, H. Yu, P. Boulet, J.-L. Dekeyser.
Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems, in: Scalable Computing: Practice and Experience (SCPE), 2009, vol. 10, n^o 2.
[17]: C. Glitia, P. Dumont, P. Boulet.
Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing, in: Multidimensional Systems and Signal Processing, 2009
http://springerlink.com/content/w3821760381l4432/?p=fc0a4428f2f4468a9d630d2a434a6f69&pi=0.
[18]: K. Ibrahim, S. Niar.
Power-aware Bus Coscheduling for Periodic Realtime Applications Running on MPSoC, in: Transactions on High-Performance Embedded Architecture and Compilation HiPeac, April 2009, vol. 2, p. 286-306.
[19]: J. Khan, S. Niar, M. Saghir, Y. El-Hillali, A. Rivenq.
Trade-off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture, in: EURASIP Journal on Embedded Systems, November 2009, vol. 2009.
[20]: I. R. Quadri, S. Meftali, J.-L. Dekeyser.
A Model based design flow for Dynamic Reconfigurable FPGAs, in: International Journal of Reconfigurable Computing, 2009.

Articles in National Peer-Reviewed Journal

[21]: A. Etien.
Business process/information system co-evolution, in: Ingénierie des Systèmes d'Information (ISI) Special issue on Evolution des systèmes d'information, 2009, vol. 14, n^o 6.

International Peer-Reviewed Conference/Proceedings

[22]: A. Abdallah, A. Gamatié, J.-L. Dekeyser.
Model-Driven Design of Embedded Multimedia Applications on SoCs, in: 12th Euromicro Conference on Digital System Design (DSD2009), Patras, Greece, August 2009.
[23]: V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.
Traceability Mechanism for Error Localization in Model Transformations, in: 4th International Conference on Software and Data Technologies (ICSOFT'2009), Sofia, Bulgaria, July 2009.
[24]: M. Baklouti, P. Marquet, M. Abid, J.-L. Dekeyser.
Study and Integration of a Parametric Neighbouring Interconnection Network in a Massively Parallel Architecture on FPGA, in: The 7th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-2009), Rabat, Morocco, may 2009.
[25]: H. Chtioui, R. Ben Atitallah, S. Niar, M. Abid, J.-L. Dekeyser.
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCs, in: 12th Euromicro Conference on Digital System Design (DSD2009), Patras, Greece, August 2009.
[26]: J.-L. Dekeyser, I. R. Quadri, A. Gamatié.
Tutorial: Using the UML profile for MARTE to MPSoC co-design dedicated to signal processing, in: Colloque International Télécom 2009 et 6èmes Journées JFMMA, Agadir, Morocco, March 2009.
[27]: A. Gamatié, H. Yu, G. Delaval, É. Rutten.
A Case Study on Controller Synthesis for Data-Intensive Embedded Systems, in: 6th IEEE Int. Conference on Embedded Systems and Software (ICESS'09), Hangzhou, China, May 2009.
[28]: C. Glitia, P. Boulet.
Interaction between inter-repetition dependences and high-level transformations in Array-OL, in: Conference on Design and Architectures for Signal and Image Processing (DASIP 2009), Sophia Antipolis, France, September 2009.
[29]: N. Harb, S. Niar, J. Khan, M. Saghir.
A Reconfigurable Platform Architecture for an Automotive Multiple-Target Tracking System, in: Proc. 2nd Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'2009), in conjunction with Esweek (CASES'09, CODES+ISSS'09, EMSOFT'09), Grenoble, France, 2009.
[30]: J. Khan, S. Niar, A. Menhaj, Y. El-Hillali.
Radar Based Collision Avoidance System Implementation in a Reconfigurable MPSoC, in: Proc. 9th International Conference on ITS Telecommunications (ITST), Lille, France, 2009.
[31]: I. R. Quadri, Y. El-Hillali, S. Meftali, J.-L. Dekeyser.
Model based design flow for implementing an Anti-Collision Radar system, in: 9th International IEEE Conference on ITS Telecommunications (ITS-T 2009), Lille, France, October 2009.
[32]: I. R. Quadri, S. Meftali, J.-L. Dekeyser.
Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs, in: International Conference on Design and Architectures for Signal and Image Processing (DASIP 09), Nice, France, September 2009.
[33]: I. R. Quadri, S. Meftali, J.-L. Dekeyser.
MARTE based design approach for targeting Reconfigurable Architectures, in: 2nd International Conference on Embedded Systems (ESC'09), Alger, Algeria, May 2009, Invited Paper.
[34]: I. R. Quadri, A. Muller, S. Meftali, J.-L. Dekeyser.
MARTE based design flow for Partially Reconfigurable Systems-on-Chips, in: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Florianapolis, Brazil, October 2009.
[35]: W. Rodrigues, F. Guyomarc'h, J.-L. Dekeyser, Y. Le Menach.
Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines, in: Compumag 2009, november 2009.
[36]: V. Rusu.
Formal Executable Semantics for Conformance in the MDE Framework, in: Proc. 2nd UML & FM Workshop, Artist NoE, 2009.
[37]: A. Tinzefte, Y. Le Menach, J. Korecki, F. Guyomarc'h.
Parallel Direct Solver For The Finite Integration Technique in Electrokinetic Problems, in: Compumag, Florianapolis, Brazil, November 2009.
[38]: R. Tligue, Y. Aydi, M. Baklouti, M. Abid, J.-L. Dekeyser.
The design methodology and the implementation of MPSOC based on Delta MINs on FPGA, in: The 21th IEEE International Conference on Microelectronics (ICM'2009), arrakech, Morocco, 2009.

National Peer-Reviewed Conference/Proceedings

[39]: A. Abdallah, A. Gamatié, J.-L. Dekeyser.
Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, in: SYMPosium en Architecture de machines (SympA'13), Toulouse, France, September 2009.

Scientific Books (or Scientific Book chapters)

[40]: A. Gamatié.
Designing Embedded Systems with the SIGNAL Programming Language: Synchronous, Reactive Specification, Springer Verlag, New York, 2009.

Internal Reports

[41]: C. Glitia, P. Boulet, É. Lenormand, M. Barreteau.
Repetitive Model Refactoring Strategy for the Design Space Exploration of Intensive Signal Processing Applications, INRIA, September 2009, n^o number not yet available, extended version.
[42]: I. R. Quadri, S. Meftali, J.-L. Dekeyser.
From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow, INRIA, France, March 2009, n^o 6862
http://hal.inria.fr/inria-00365061/en/, Research Report.

References in notes

[43]: IEEE (editor)
Std 1076-1993 IEEE Standard VHDL Language, Reference Manual - Description, Inst of Elect & Electronic, 1994.
[44]: Acceleo, 2009
http://www.acceleo.org.
[45]: Object Management Group, Inc. (editor)
U2 Partners' (UML 2.0): Superstructure, 2nd revised submission, January 2003
http://www.omg.org/cgi-bin/doc?ptc/03-01-02.
[46]: Object Management Group, Inc. (editor)
(UML 2.0): Superstructure Draft Adopted Specification, July 2003
http://www.omg.org/cgi-bin/doc?ptc/03-07-06.
[47]: C. André, F. Mallet, R. de Simone.
Time Modeling in MARTE, in: ECSI Forum on specification & Design Languages (FDL), Barcelona Espagne, ECSI, 2007, p. 268-273
http://hal.inria.fr/inria-00204481/en/.
[48]: C. Bastoul.
Code Generation in the Polyhedral Model Is Easier Than You Think, in: PACT'13 IEEE International Conference on Parallel Architecture and Compilation Techniques, Juan-les-Pins, September 2004, p. 7–16.
[49]: R. Ben Atitallah, É. Piel, S. Niar, P. Marquet, J.-L. Dekeyser.
Multilevel MPSoC simulation using an MDE approach, in: IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, September 2007
http://www2.lifl.fr/west/publi/BPT+07.pdf.
[50]: A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.
The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003, vol. 91, n^o 1, p. 64-83.
[51]: A. E. H. Benyamina, P. Boulet.
Multi-objective Mapping for NoC Architecture, in: Journal of Digital Information Management, December 2007, vol. 5, n^o 6, p. 378–384.
[52]: P. Boulet.
Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, INRIA, February 2007, n^o RR-6113
http://hal.inria.fr/inria-00128840/en, Research Report.
[53]: P. Boulet.
Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing, INRIA, March 2008, n^o RR-6467
http://hal.inria.fr/inria-00261178/en/, Research Report.
[54]: P. Boulet, J.-L. Dekeyser, J.-L. Levaire, P. Marquet, J. Soula, A. Demeure.
Visual Data-parallel Programming for Signal Processing Applications, in: 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy, February 2001, p. 105–112.
[55]: P. Caspi, D. Pilaud, N. Halbwachs, J.A. Plaice.
Lustre: a declarative language for real-time programming, in: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (POPL'87), ACM Press, 1987, p. 178-188.
[56]: A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J.-C. Dufourd, J.-L. Marro.
Array-OL : Proposition d'un Formalisme Tableau pour le Traitement de Signal Multi-Dimensionnel, in: Gretsi, Juan-Les-Pins, France, September 1995.
[57]: A. Demeure, Y. Del Gallo.
An Array Approach for Signal Processing Design, in: Sophia-Antipolis conference on Micro-Electronics (SAME 98), France, October 1998.
[58]: P. Dumont, P. Boulet.
Transformations de code Array-OL : implémentation de la fusion de deux tâches, Laboratoire d'Informatique fondamentale de Lille et Thales Communications, October 2003, Technical report.
[59]: P. Dumont.
Étude des Transformations d'un Code Array-OL dans Gaspard, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, France, September 2002, n^o 02-11
http://www.lifl.fr/LIFL1/publications/2002-11.ps, Research Report.
[60]: P. Dumont.
Spécification multidimensionnelle pour le traitement du signal systématique, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, 2005, (In French).
[61]: Eclipse Consortium.
The Eclipse Project, 2003
http://www.eclipse.org.
[62]: Eclipse Consortium.
EMF Eclipse Modeling Framework, 2007
http://www.eclipse.org/emf.
[63]: D. D. Gajski, R. Kuhn.
Guest Editor Introduction: New VLSI-Tools, in: IEEE Computer, December 1983, vol. 16, n^o 12, p. 11-14.
[64]: I. Galvão, A. Goknil.
Survey of Traceability Approaches in Model-Driven Engineering, in: IEEE International Enterprise Distributed Object Computing Conference (EDOC 2007), October 2007, p. 313-326.
[65]: F. Glitia, A. Etien, C. Dumoulin.
Traceability for an MDE Approach of Embedded System Conception, in: Fourth ECMDA Tracibility Workshop, Berlin, Germany, June 2008.
[66]: C. Glitia.
Code transformations for systematic signal processing and memory size optimizations, Université des sciences et technologies de Lille, 2006, Master recherche.
[67]: F. Jouault.
Loosely Coupled Traceability for ATL, in: European Conference on Model Driven Architecture (ECMDA) workshop on traceability, 2005, p. 29–37.
[68]: A. Koudri, D. Aulagnier, J. Champeau.
FPGA design based on UML/MDA Approach: Application to an RF Tranceiver development, in: 4th workshop on tUML for SoC Design, June 2007.
[69]: A. Koudri, D. Aulagnier, J. Champeau.
Une sémantique opérationnelle pour une meilleure métamodélisation, in: Atelier sur la Sémantique des Modèles, march 2007.
[70]: S. Le Beux, P. Marquet, J.-L. Dekeyser.
Model Driven Engineering Benefits for High Level Synthesis, INRIA, 2008, n^o 6615
http://hal.inria.fr/inria-00311300/en/, Research report.
[71]: P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.
Polychrony for System Design, in: Journal for Circuits, Systems and Computers, April 2003, vol. 12, n^o 3, p. 261–304.
[72]: A. Meena, P. Boulet.
Model Driven Scheduling Framework for Multiprocessor SoC Design, in: Workshop on Scheduling for Parallel Computing, SPC 2005, Poznan, Poland, September 2005
http://www.cs.put.poznan.pl/mdrozdowski/spc-ppam05/.
[73]: A. Meena.
Allocation, Assignation et ordonnancement pour les systèmes sur puce multi-processeurs, Université des Sciences et Technologies de Lille, December 2006, Doctorat en Informatique.
[74]: J.-M. Mottu, B. Baudry, Y. Le Traon.
Mutation Analysis Testing for Model Transformations, in: proceedings of the European Conference on Model Driven Architecture (ECMDA 06), Bilbao, Spain, July 2006.
[75]: Object Management Group, Inc..
Meta Object Facility (MOF) Core Specification, Version 2.0, January 2006
http://www.omg.org.
[76]: Object Management Group, Inc..
MOF Query / Views / Transformations, July 2007
http://www.omg.org, OMG paper.
[77]: OpenMP Architecture Review Board.
OpenMP Application Programme Interface, May 2005
http://www.openmp.org/drupal/mp-documents/spec25.pdf.
[78]: Open SystemC Initiative.
SystemC, 2002
http://www.systemc.org/.
[79]: D. Schmidt.
Model-Driven Engineering, in: IEEE Computer, February 2006, vol. 39, n^o 2, p. 41-47.
[80]: J. Soula.
Principe de Compilation d'un Langage de Traitement de Signal, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, December 2001, (In French).
[81]: J. Taillard, F. Guyomarc'h, J.-L. Dekeyser.
A Graphical Framework for High Performance Computing using an MDE Approach, in: 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Toulouse, France, February 2008, to appear.
[82]: Donald E. Thomas, Philip R. Moorby.
The Verilog Hardware Description Language, Fourth, Kluwer Academic Publishers, May 1998.
[83]: Y. Velegrakis, R. J. Miller, J. Mylopoulos.
Representing and Quering Data transformations, in: International conference on Data Engineering (ICDE), April 2005, p. 81-92.
[84]: H. Yu, A. Gamatié, É. Rutten, J.-L. Dekeyser.
13, in: Model Transformations from a Data Parallel Formalism towards Synchronous Languages, Springer Verlag, 2008.

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