Section: Overall Objectives

Highlights of 2009

Compsys has continued its activities on static single assignment (SSA) and register allocation, in collaboration with STMicroelectronics, but working more deeply on just-in-time compilation, in particular on the developments of code optimizations algorithms that take into account speed and memory footprint. This work has led to three new developments:

• An algorithm for out-of-SSA conversion that improves previous approaches in all aspects: it is provably correct, more general, easier to implement, faster, and less memory-consuming. This algorithm, developed by Benoit Boissinot, Alain Darte, Fabrice Rastello, and other colleagues from stm icroelectronics, was presented at the IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2009) and received the best paper award (third year in a row for the Compsys team, which seems extremely rare, if not unique, in any conference).

• A debunking work on static single information (SSI), which is an extension of SSA: in particular it provides a correct ordering of basic blocks for which live-ranges of variables form intervals. This work is the result of an informal collaboration of Benoit Boissinot, Alain Darte, and Fabrice Rastello with Philip Brisk from the EPFL, Lausanne.

• A technique for moving parallel copies between registers, particularly useful to be able to apply SSA-based register allocation even to control-flow graphs with “critical edges”.

The Sceptre Minalogic project was finished and (very) positively evaluated at the end of 2009. The first implementation of a full SSA-based register allocator, with two phases (spilling + coloring/coalescing), was done by Quentin Colombet. Florent Bouchez defended his PhD in May 2009 on this topic. Alain Darte and Fabrice Rastello participated to a tutorial on “SSA-based register allocation” at CGO'09. This tutorial was given again at LCPC'09 by Florent Bouchez and Fabrice Rastello. The first (international) workshop focusing on SSA was co-organized by Fabrice Rastello, with the help of Alain Darte and Benoit Boissinot, at Autrans in April 2009. The Sceptre project will continue through Mediacom, a new 3-years project funded by Nano2012 (governmental help for R&D).

In high-level synthesis, two aspects have been explored:

• High-level transformations for improving performances and optimizing communications, in particular by analyzing the industrial tool Altera C2H. A joint project with the Cairn Inria project has started, in collaboration with stm icroelectronics, on source-to-source transformations for high-level synthesis (S2S4HLS), also funded within Nano2012. A collaboration is also in progress with all french specialists on HLS, which should lead to an ANR proposal.

• Program termination and worst-case computational complexity, i.e., briefly speaking an evaluation of the number of iterations in looping processes such as codes with while loops and jumps (abstract worse-case execution time). The initial motivation of this research, which is part of the S2S4HLS project, was to be able to analyze/transform codes with while loops so that they can be accepted by HLS tools. The main result, unexpected because surprising, is that we can reuse, for an apparently-disconnected topic (program termination), all polyhedral tools developed in high-performance computing: our multi-dimensional scheduling techniques and the mathematical tools for manipulating polyhedra and counting integer points within polyhedra.