Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

[1]

F. Bouchez.
A Study of Spilling and Coalescing in Register Allocation as Two Separate Phases, École normale supérieure de Lyon, April 2009, Ph. D. Thesis.

Articles in International Peer-Reviewed Journal

[2]

P. Grosse, Y. Durand, P. Feautrier.
Methods for Power Optimization in SOC-Based Data Flow Systems, in: ACM Transactions on Design Automation of Electronic Systems, 2009, vol. 14, n^o 3, p. 1-20
http://doi.acm.org/10.1145/1529255.1529260.

Invited Conferences

[3]

F. Bouchez, F. Rastello.
SSA-Based Register Allocation, in: The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC'09), Newark, Delaware, October 2009, Tutorial with P. Brisk, S. Hack, and J. Palsberg.

[4]

A. Darte, F. Rastello.
SSA-Based Register Allocation, in: International Symposium on Code Generation and Optimization (CGO'09), Seattle, March 2009, Tutorial with P. Brisk and J. Palsberg.

[5]

P. Feautrier.
The Polytope Model, Past, Present, Future, in: The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC'09), Newark, Delaware, October 2009, Keynote address.

International Peer-Reviewed Conference/Proceedings

[6]

B. Boissinot, A. Darte, B. Dupont de Dinechin, C. Guillon, F. Rastello.
Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency, in: International Symposium on Code Generation and Optimization (CGO'09), Seattle, WA, USA, IEEE Computer Society Press, March 2009, p. 114–125, Best paper award.

[7]

B. Diouf, A. Cohen, F. Rastello, J. Cavazos.
Split Register Allocation: Linear Complexity Without the Performance Penalty, in: International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'10), Lecture Notes in Computer Science, Springer Verlag, January 2010, to appear.

[8]

O. Labbani, P. Feautrier, E. Lenormand, M. Barreteau.
Elementary Transformation Analysis for Array-OL, in: ACS/IEEE International Conference on Computer Systems and Applications (AICCSA'09), Rabat, Morocco, May 2009, p. 362-367.

[9]

Q. Lu, C. Alias, U. Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, Y. Chen, H. Lin, T.-F. Ngai.
Data Layout Transformation for Enhancing Locality on NUCA Chip Multiprocessors, in: International ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT'09), September 2009.

[10]

M. Rastello, F. Rastello, H. Bellot, F. Ousset, F. Dufour.
Size of Snow Particles in a Powder-Snow Avalanche, in: ASME Fluids Engineering Division Summer Meeting 2009 (FEDSM'09), August 2009.

Workshops without Proceedings

[11]

B. Boissinot.
Fast Liveness Checking in SSA, in: SSA form seminar, Autrans, April 2009.

[12]

A. Darte.
Out-of-SSA Translation, in: Workshop Compilers for Parallel Computing, Zurich, Switzerland, January 2009.

[13]

A. Darte.
Out-of-SSA Translation, in: SSA form seminar, Autrans, April 2009.

References in notes

[14]

P. Boulet, P. Feautrier.
Scanning Polyhedra without DO loops, in: PACT'98, October 1998.

[15]

A. Darte, R. Schreiber.
System and Method of Optimizing Memory Usage with Data Lifetimes, April 2008, US patent number 7363459.

[16]

A. Darte, R. Schreiber, G. Villard.
Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, n^o 10, p. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.

[17]

Benoît. Dupont de Dinechin, C. Monat, F. Rastello.
Parallel Execution of the Saturated Reductions, in: Workshop on Signal Processing Systems (SIPS 2001), IEEE Computer Society Press, 2001, p. 373-384.

[18]

P. Feautrier.
Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, n^o 5, p. 459–487.

[19]

P. Feautrier.
Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, n^o 1, p. 23–53.

[20]

P. Feautrier.
Some Efficient Solutions to the Affine Scheduling Problem, Part II, Multidimensional Time, in: International Journal of Parallel Programming, December 1992, vol. 21, n^o 6.

[21]

R. W. Floyd.
Assigning Meaning to Programs, in: Proc. Symp. on Applied Mathematics, J. T. Schwartz (editor), AMS, 1967, vol. 19.

[22]

A. Fraboulet, K. Godary, A. Mignotte.
Loop Fusion for Memory Space Optimization, in: IEEE International Symposium on System Synthesis, Montréal, Canada, IEEE Press, October 2001, p. 95–100.

[23]

R. Johnson, M. Schlansker.
Analysis of Predicated Code, in: Micro-29, International Workshop on Microprogramming and Microarchitecture, 1996.

[24]

A. Stoutchinin, F. De Ferrière.
Efficient Static Single Assignment Form for Predication, in: International Symposium on Microarchitecture, ACM SIGMICRO and IEEE Computer Society TC-MICRO, 2001.

[25]

A. Turjan, B. Kienhuis, E. Deprettere.
Translating affine nested-loop programs to process networks, in: CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, New York, NY, USA, ACM, 2004, p. 220–229.

[26]

S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.
Improved derivation of process networks, in: Proceedings of the 4th International Workshop on Optimization for DSP and Embedded Systems (ODES'06, 2006.