Team Cairn

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities

Section: Overall Objectives


This year, we developed an automatic generation tool for efficient and accurate hardware, on FPGAs or ASICs, evaluation of elementary functions such as reciprocal, square-root, trigonometric, hyperbolic, powers, etc. The obtained circuits are small, fast, and have a low-power consumption. They also provide a good accuracy with bounded maximal error (bounds can be validated using a proof assistant program) or small average error. See Section 6.1.2 .

We have defined an original generic approach to the automatic generation of processor reconfigurable extensions and application compilation on these new architectures based on constraints programming. As a result, the two systems UPAK and DURASE were developed and presented at the University Booth of DATE 2009 conference. See Section 6.2.1 .

In the fixed-point conversion from floating-point process, one of the main challenge is to evaluate the specification accuracy. We have therefore defined an analytical approach for accuracy estimation of fixed-point embedded systems that allows to obtain precise estimates, much faster than using simulations, the state-of-art approach for this issue. We also defined an automatic floating-point to fixed-point conversion methodology which has been integrated, this year, into an open-source compilation and synthesis framework, and which will be used by companies such as STMicroelectronics. See Section .

This year has seen the design and fabrication of an integrated circuit prototype (Ochre: a circuit for On-Chip Randomness Extraction) including our architecture proposal for hybrid random number generator (RNG) [15] . The chip is composed of a TRNG (True RNG) based on several free-running ring-oscillators, a cellular automata PRNG (Pseudo RNG) and some hardware statistical tests including the FIPS 140-2. The tests monitor the TRNG quality in real time to validate the PRNG seed randomness as proposed in [66] . Ochre has been fabricated in a 130 nm CMOS technology from STMicrocelectronics and is able to reach 800 Mbit/s for 0.3mm2 and 5mW at 200MHz. The circuit has been successfully tested after fabrication. See Section 6.3.7 .

Adeel Pasha has won the "Best Student Paper Award" at IEEE INMIC2009 for his paper "Toward Ultra Low-Power Hardware Specialization of a Wireless Sensor Network Node".


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