Interconnect Explorer: a High-Level Power and Delay Estimation Tool for On-Chip Interconnects
Participants : Antoine Courtay [ correspondant ] , Olivier Sentieys, Johann Laurent [ Lab-Sticc, Lorient ] .
In today's s oc s, interconnects introduce delays and consume power and chip resources. A tool, called Interconnect Explorer, has been developed for high-level estimation of interconnect performance which provides fast and accurate figures for both time and power consumption  . These results allowed us to determine new key issues that have to be taken into account for future performance optimizations. This tool is based on energy and timing multi-input tables obtained from transistor-level simulations. The tool can be configured by setting the following parameters: technology, metal layer, bus length, bus width, frequency, and bufferization type. Interconnect Explorer provides users with results in terms of energy consumption, static power consumption, average dynamic power consumption, maximum dynamic power consumption, instantaneous dynamic power consumption, maximum frequency allowed on the bus, area of the bus (wires and buffers), commutation rate per bit and percentage of appearance of each type of transitions. The maximum error between consumption results provided by Interconnect Explorer and SPICE simulation is less than 6%. Interconnect Explorer provides results instantaneously (less than 1 second computation) whereas a SPICE simulation of the same configuration takes several hours.