Team Cairn

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Scientific Foundations
Application Domains
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Section: Scientific Foundations

Dynamically and Heterogeneous Reconfigurable Platforms

One available technology for building reconfigurable systems is the field-programmable gate arrays (fpga ) introduced to the market in the mid 1980s. Today's components feature millions of gates of programmable logic, and they are dense enough to host complete computing systems on a programmable chip. These fpga s have been the reconfigurable computing mainstream for a couple of years and achieve flexibility by supporting gate-level reconfigurability, e.g. they can be fully optimized for any application at the bit level. However, their flexibility is achieved at a very important interconnection cost. To be configured, a large amount of data must be distributed via a slow serial programming process to all the processing and interconnection resources. Configurations must be stored in an external memory. These interconnection and configuration overheads lead to energy inefficient architectures.

To increase optimization potential of programmable processors without the fpga s penalties, the functional-level reconfiguration was introduced. Reconfigurable Processors are the most advanced class of reconfigurable architectures. The main concern of this class of architectures is to support flexibility while reducing reconfiguration overhead. Precursors of this class were the KressArray [99] , RaPid [96] , and RaW machines [120] which were specifically designed for streaming algorithms. Morphosys [104] , Remarc [109] or Adres [94] contain programmable ALUs with a reconfigurable interconnect. These works have led to commercial products such as the Extreme Processor Platform (XPP) [86] from PACT, Bresca [112] from Silicon Hive, designed mainly for telecommunication applications.

Another strong trend towards heterogeneous reconfigurable processors can be observed. Hybrid architectures combine standard gpp or dsp cores with arrays of field-configurable elements . These new reconfigurable architectures are entering the commercial market. Some of their benefits are the following: functionality on demands (set-top boxes for digital TV equipped with decoding hardware on demand), acceleration on demand (coprocessors that accelerate computationally demanding applications in multimedia, communications applications), and shorter time to market (products that target asic platforms can be released earlier using reconfigurable hardware).

Dynamic reconfiguration allows an architecture to adapt itself to various incoming tasks. This requires complex management and control which can be provided as services of a real-time operating system (RTOS) [105] : communication, memory management, task scheduling [92] [89] and task placement [84] . Such an Operating System (OS) approach has many advantages: it is a complete design framework, independent of the technology and of the hardware architecture, thus helping to drastically reduce the design time of the complete platform.

Communications in a reconfigurable platform is also a very important research subject. The role of communication resources is to support transactions between the different components of the platform, either between macro-components of the platform – main processor, dedicated modules, dynamically reconfigurable parts of the platform – or inside the elements of the reconfigurable parts themselves. This has motivated studies on Networks on Chip for Reconfigurable s oc s [88] [111] that trade flexibility and quality of service.


In Cairn we mainly target reconfigurable system-on-chip (RSoC) defined as a set of computing and storing resources organized around a flexible interconnection network and integrated onto a single silicon chip (or programmable chip such as FPGAs). The architecture is specialized for an application domain, and the flexibility is featured by hardware reconfiguration and software programmability. Therefore, computing resources are heterogeneous and we focus on the following: