Bibliography

Major publications by the team in recent years

[1]

L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, n^o 3.

[2]

A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, n^o 1, p. 21-33.

[3]

R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.

[4]

S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, p. 10–18, Best Paper Award.

[5]

L. Imbert, A. Peirera, A. Tisserand.
A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, F. T. Luk (editor), SPIE, San Diego, California, U.S.A., August 2007, vol. 6697, n^o 66970N, p. 1–9
http://dx.doi.org/10.1117/12.733652.

[6]

K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, n^o 12-15.

[7]

D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, n^o 1, p. 1–15.

[8]

D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.

[9]

S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, p. 1-13, Article ID 562326, 13 pages.

[10]

C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, n^o 6.

[11]

A. Tisserand.
High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, n^o 1, p. 14–23
http://dx.doi.org/10.1504/IJHPSA.2007.013288, invited paper.

[12]

C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, n^o 4-6.

Publications of the year

Doctoral Dissertations and Habilitation Theses

[13]

F. B. Abdallah.
Étude et optimisation de l'interaction processeurs-architectures reconfigurables dynamiquement, Study and optimisation of dynamically reconfigurable architectures - processors interaction , University of Rennes 1, ENSSAT and University of Tunis, ENIT, October 2009, Ph. D. Thesis.

[14]

T.-D. Nguyen.
Cooperative MIMO Strategies for Energy Constrained Wireless Sensor Networks, University of Rennes 1, ENSSAT, May 2009, Ph. D. Thesis.

[15]

R. Santoro.
Vers des générateurs de nombres aléatoires uniformes et gaussiens à très haut débit, Towards High-Rate Uniform and Gaussian Random Number Generators , University of Rennes 1, ENSSAT and Laval University, Québec, CA, December 2009, Ph. D. Thesis.

Articles in International Peer-Reviewed Journal

[16]

D. Chillet, S. Pillement, O. Sentieys.
Real-Time Scheduling on Heterogeneous SoC Architectures Using Inhibitor Neurons in a Neural Network, in: Journal of Systems Architecture, 2009, Submitted.

[17]

A. Courtay, J. Laurent, O. Sentieys.
Spatial Switching data coding technique analysis and improvements for interconnect power consumption optimization, in: Journal of Low Power Electronics (JOLPE), 2009, Submitted.

[18]

L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, D. Demigny.
Flexible interconnection network for dynamically and partially reconfigurable architectures, in: International Journal on Reconfigurable Computing (IJRC), 2010, to appear.

[19]

J. Lallet, S. Pillement, O. Sentieys.
Efficient and Flexible Dynamic Reconfiguration for Multi-Context Architectures, in: Journal of Integrated Circuits and Systems, 2009, vol. 4, n^o 1, p. 36-44.

[20]

B. Miramond, E. Huck, F. Verdier, A. Benkhelifa, B. Granado, M. Aichouch, J. C. Prevotet, D. Chillet, S. Pillement.
OveRSoC : a Framework for the Exploration of RTOS for RSoC Platforms, in: International Journal of Reconfigurable Computing, 2009, Submitted.

[21]

T. Nguyen, O. Berder, O. Sentieys.
Energy efficient cooperative strategies for infrastructure to vehicle communications, in: IEEE Transactions on Intelligent Transportation Systems, 2010, Submitted.

[22]

S. Piestrak.
A note on RNS architectures for the implementation of the diagonal function, in: Information Processing Letters, 2009, Submitted.

[23]

S. Piestrak, S. Pillement, O. Sentieys.
Comments on 'A low-power dependable Berger code for fully asymmetric communication', in: IEEE Communications Letters, 2009, Submitted.

[24]

S. Piestrak, S. Pillement, O. Sentieys.
On designing efficient codecs for bus-invert Berger code for fully asymmetric communication, in: IEEE Transactions on Circuits and Systems II, 2009, Submitted.

[25]

S. Pillement, J. Philippe, O. Sentieys.
Spatio-temporal Coding to Improve Speed and Noise Tolerance of On-chip Interconnect, in: MicroElectronics Journal, 2010, to appear.

[26]

R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Accuracy Evaluation of Fixed-Point based LMS Algorithm, in: Digital Signal Processing, 2010, to appear.

[27]

C. Wolinski, K. Kuchcinski, E. Raffin.
Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Transactions on Design Automation of Electronic Systems, 2010, to appear.

Articles in National Peer-Reviewed Journal

[28]

D. Chillet, S. Pillement, O. Sentieys.
Ordonnancement de tâches par réseaux de neurones pour architectures de SoC hétérogènes, in: Traitement du signal, 2009, vol. 26, n^o 1, p. 77-89.

Invited Conferences

[29]

O. Berder.
CAPTIV : Consommation et strAtégies cooPératives pour les Transmissions entre infrastructures et Véhicules, in: Congrès international ATEC - ITS France, Versailles, France, February 2009.

[30]

A. Tisserand.
Low-Power Arithmetic Operators, in: Proc. of the 8ème journées d'études Faible Tension Faible Consommation, Neuchâtel, Switzerland, June 2009.

[31]

A. Tisserand.
Opérateurs arithm'etiques sécurisés, in: 3ème Rencontres Arithmétique de l'Informatique Mathématique (RAIM), October 2009.

[32]

C. Wolinski, K. Kuchcinski, K. Martin, R. Raffin, F. Charot.
How constraints programming can help you in the generation of optimized application specific reconfigurable processor extension, in: Proc. of the International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, Las Vegas, Nevada, USA, July 2009.

International Peer-Reviewed Conference/Proceedings

[33]

E. Casseau, B. L. Gal.
High-Level Synthesis for the Design of FPGA-based Signal Processing Systems, in: Proc. of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), Samos, Greece, July 2009, p. 25-32.

[34]

R. Chokshi, A. Shrivastava, K. S. Berezowski, S. J. Piestrak.
Exploiting residue number system for power-efficient digital signal processing in embedded processors, in: Proc. of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, ACM, October 2009, p. 19-28.

[35]

S. Collange, D. Defour, A. Tisserand.
Power Consumption of GPUs from a Software Perspective, in: Proc. of the 9th International Conference on Computational Science (ICCS), Baton Rouge, Louisiana, U.S.A., Lecture Notes in Computer Science (LNCS), Springer-Verlag, May 2009, vol. 5544, p. 914–923.

[36]

A. Courtay, J. Laurent, O. Sentieys, N. Julien.
Interconnect Explorer: A High-level Power Estimation Tool for On-Chip Interconnects, in: Proc. of the IEEE/ACM Design Automation Conference (DAC), User Track, San Francisco, USA, 2009.

[37]

A. Courtay, J. Laurent, O. Sentieys, N. Julien.
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses, in: Proc. of the IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, Lecture Notes in Computer Science (LNCS), Springer-Verlag, March 2009, vol. 5349, p. 359–368.

[38]

A. Courtay, J. Laurent, O. Sentieys, N. Julien.
On-chip interconnects energy consumption: High-level estimation and architectural optimizations, in: PhD forum of IEEE/ACM Design, Automation & Test in Europe Conference, DATE'09, Nice, France, 2009.

[39]

F. Demangel, N. Fau, N. Drabik, F. Charot, C. Wolinski.
A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications, in: Proc. of the IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, DATE '09, Nice, France, April 2009, p. 1242-1245.

[40]

L. Devaux, D. Chillet, S. Pillement, D. Demigny.
Flexible Communication Support For Dynamically Reconfigurable FPGA, in: Proc. of the Southern Programmable Logic Conference, Sao-Carlos, Brazil, April 2009, p. 65-70.

[41]

L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, D. Demigny.
DRAFT: Flexible Interconnection Network for Dynamically Reconfigurable Architectures, in: Proc. of the IEEE International Conference on Field-Programmable Technology (FPT'09), Sydney, Australia, IEEE, December 2009.

[42]

M. Djendi, A. Gilloire, P. Scalart.
Comparative study of new blind source separation structures for two-channel acoustic noise cancellation, in: Proc. of the XVII European Signal and Image Processing Conference (EUSIPCO'09), Glascow, Scotland, EURASIP, August 2009.

[43]

B. L. Gal, E. Casseau.
Automated Multimode System Design for High Performance DSP Applications, in: Proc. of the European Signal and Image Processing Conference (EUSIPCO), Glascow, Scotland, EURASIP, August 2009.

[44]

P. Giorgi, T. Izard, A. Tisserand.
Comparison of Modular Arithmetic Algorithms on GPUs, in: Proc. of the International Conference on Parallel Computing (ParCo), Lyon, France, September 2009.

[45]

S. M. A. H. Jafri, S. J. Piestrak, O. Sentieys.
Design of a fault-tolerant coarse-grained reconfigurable architecture: A case study, in: Proc. of the 11th IEEE International Symposium on Quality Electronic Design (ISQED 2010), San Diego, CA, USA, IEEE, March 2010, - p, to appear.

[46]

S. Khan, E. Casseau, D. Menard.
Reconfigurable SWP Operator for Multimedia Processing, in: Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, IEEE Computer Society, 2009, p. 199-202.

[47]

S. Khan, E. Casseau, D. Menard.
SWP for multimedia operator design, in: Proc. of the Conference on Sciences of Electronic, Technologies of Information and Telecommunications, SETIT, Hammamet, Tunisia, March 2009.

[48]

J. Lallet, S. Pillement, O. Sentieys.
xMAML: a Modeling Language for Dynamically Reconfigurable Architectures, in: Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Patras, Greece, August 2009, p. 680 - 687
http://dx.doi.org/10.1109/DSD.2009.151.

[49]

L. Lepauloux, P. Scalart, C. Marro.
An efficient low-complexity algorithm for crosstalk-resistant adaptive noise canceller, in: Proc. of the XVII European Signal and Image Processing Conference (EUSIPCO'09), Glascow, Scotland, EURASIP, August 2009.

[50]

K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint-Driven Identification of Application Specific Instructions in the DURASE system, in: Proc. of Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, Lecture Notes in Computer Science, Springer, July 2009, vol. 5657, p. 194-203.

[51]

K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system, in: Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, IEEE Computer Society, July 2009, p. 145-152.

[52]

D. Menard, E. Casseau, S. Khan, O. Sentieys, S. Chevobbe, S. Guyetant, R. David.
Reconfigurable Operator Based Multimedia Embedded Processor, in: Proc. of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications, Lecture Notes in Computer Science, Springer, 2009, vol. 5453, p. 39–49.

[53]

Q.-T. Ngo, O. Berder, P. Scalart.
3-D minimum Euclidean distance based sub-optimal precoder for MIMO spatial multiplexing systems, in: Proc. of IEEE International Conference on Communications (ICC), Cape Town, South Africa, June 2010, to appear.

[54]

Q.-T. Ngo, O. Berder, B. Vrigneau, O. Sentieys.
Minimum Distance Based Precoder for MIMO-OFDM Systems Using a 16-QAM Modulation, in: Proc. of the IEEE International Conference on Communications (ICC), Dresden, Germany, June 2009, p. 1–5.

[55]

T.-D. Nguyen, O. Berder, O. Sentieys.
Cooperative strategies comparison for infrastructure and vehicle communications in CAPTIV, in: Proc. of the 9th International Conference on ITS Telecommunication (ITST), Lille, France, October 2009.

[56]

H. Nguyen, D. Menard, O. Sentieys.
Design of Optimized Fixed-point WCDMA Receiver, in: Proc. of the XVII European Signal and Image Processing Conference (EUSIPCO'09), Glascow, Scotland, EURASIP, August 2009.

[57]

H.-N. Nguyen, D. Menard, O. Sentieys.
Dynamic Precision Scaling for Low Power WCDMA Receiver, in: Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, May 2009, p. 205-208.

[58]

K. Parashar, R. Rocher, D. Menard, O. Sentieys.
A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems, in: Proc. of the 23rd International Conference on VLSI Design, Bangalore, India, January 2010, to appear.

[59]

M. A. Pasha, S. Derrien, O. Sentieys.
Toward Ultra Low-Power Hardware Specialization of a Wireless Sensor Network Node, in: Proc. of the 13th IEEE International Multitopic Conference, INMIC 2009, Islamabad, Pakistan, December 2009.

[60]

M. A. Pasha, S. Derrien, O. Sentieys.
Ultra Low-Power FSM for Control Oriented Applications, in: Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, May 2009, p. 1577 - 1580.

[61]

M. Pham, S. Pillement, D. Demigny.
A Fault-Tolerant Layer For Dynamically Reconfigurable Multi-Processor System-On-Chip, in: Proc. of the International Conference on ReConFigurable Computing and FPGAs, ReConFig'09, Cancun, Mexico, December 2009.

[62]

M. Pham, S. Pillement, D. Demigny.
Reconfigurable ECU Communications in Autosar Environment, in: Proc. of the 9th International Conference on ITS Telecommunications, Lille, France, October 2009.

[63]

S. Pillement, D. Chillet, Y. Oliva, J. C. Prevotet.
High-Level Exploration for Dynamic Reconfiguration Management, in: Proc. of the International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, Las Vegas, Nevada, USA, CSREA Press, July 2009.

[64]

S. Pillement, D. Chillet.
High-level Model of Dynamically Reconfigurable Architectures, in: Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Nice, France, September 2009.

[65]

R. Santoro, O. Sentieys, S. Roy.
On-Line Monitoring of Random Number Generators for Embedded Security, in: Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, May 2009, p. 3050 - 3053
http://dx.doi.org/10.1109/ISCAS.2009.5118446.

[66]

R. Santoro, O. Sentieys, S. Roy.
On-the-Fly Evaluation of FPGA-Based True Random Number Generator, in: Proc. of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI'09, Tampa, Florida, USA, May 2009, p. 55-60
http://dx.doi.org/10.1109/ISVLSI.2009.33.

[67]

R. Santoro, A. Tisserand, O. Sentieys, S. Roy.
Arithmetic operators for on-the-fly evaluation of TRNGs, in: Proc. of the Advanced Signal Processing Algorithms, Architectures and Implementations XVIII, San Diego, CA, USA, SPIE, August 2009, vol. 7444, p. 1–12.

[68]

A. Tisserand.
Function Approximation based on Estimated Arithmetic Operators, in: Proc. of the 43th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, U.S.A., IEEE, October 2009.

[69]

C. Wolinski, K. Kuchcinski, E. Raffin, F. Charot.
Architecture-Driven Synthesis of Reconfigurable Cells, in: Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Patras, Greece, September 2009, p. 531 - 538
http://dx.doi.org/10.1109/DSD.2009.183.

National Peer-Reviewed Conference/Proceedings

[70]

L. Devaux, S. B. Sassi, S. Pillement, D. Chillet, D. Demigny.
Réseau d'interconnexion flexible pour architecture reconfigurable dynamiquement et partiellement, in: Proc. of the Symposium en Architecture de machines (SympA'13), Toulouse, France, September 2009.

[71]

H. Dubois, O. Berder, G. Garnier, B. Vrigneau, O. Sentieys.
Architecture optimisée de SVD pour le calcul d'un précodeur dans une chaine de transmission MIMO., in: Proc. of the 22nd Symposium on Signal and Image Processing (GRETSI), Dijon, France, September 2009, p. 301–304.

[72]

A. Eiche, D. Chillet, S. Pillement, O. Sentieys.
Flot d'ordonnancement pour architecture reconfigurable, in: Proc. of the Symposium en Architecture de machines (SympA'13), Toulouse, France, September 2009.

[73]

J. Lallet, S. Pillement, O. Sentieys.
Plate-forme de Conception d'Architectures Reconfigurables Dynamiquement pour le Domaine du TSI, in: Proc. of the 22nd Symposium on Signal and Image Processing (GRETSI), September 2009, p. 210-215.

[74]

K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Sélection automatique d'instructions et ordonnancement d'applications basés sur la programmation par contraintes, in: Proc. of the Symposium en Architecture de machines (SympA'13), Toulouse, France, September 2009.

Workshops without Proceedings

[75]

C. Beaumin-Palud.
Gestion de la mémoire pour la réutilisation de pixels dans les algorithmes d'estimation de mouvement, in: National Workshop of the GdR SoC-SiP (System-On-Chip & System-In-Package), Paris, France, June 2009.

[76]

O. Berder.
CAPTIV : Consommation et strAtégies cooPératives pour les Transmissions entre infrastructures et Véhicules, in: Première Conférence Francophone sur les Technologies de l'Information, de la Communication et de la Géolocalisation dans les Systèmes de Transports (CoGIST), Saint-Quay-Portrieux, France, June 2009.

[77]

K. Martin.
Extraction automatique d'instructions spécialisées en utilisant la programmation par contraintes, in: National Workshop of the GdR SoC-SiP (System-On-Chip & System-In-Package), Paris, France, June 2009.

[78]

K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.
Design of Processor Accelerators with Constraints, in: SweConsNet Workshop, Linkoping, Sweden, 2009.

[79]

Y. Oliva-Venegas, J.-C. Prevotet, F. Nouvel, S. Pillement, D. Chillet.
Exploration for Dynamic Reconfiguration Management, in: Sophia Antipolis MicroElectronics Forum, SAME 2009, September 2009.

[80]

R. Santoro.
Evaluation of TRNGs under Various Experimental Conditions, in: 7th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices, June 2009.

[81]

R. Santoro.
Évaluation de TRNG dans diverses conditions expérimentales, in: Crypto'Puces, July 2009.

[82]

A. Tisserand.
Redundant Number Systems for Reconfigurable Arithmetic Units, in: 7th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices, June 2009.

References in notes

[83]

AIS 31: Functionality Classes and Evaluation Methodology for Physical Random Number Generators. Version 1 (25.09.2001) (mandatory if a German IT security certificate is applied for; English translation), 2001.

[84]

A. Ahmadinia, C. Bobda, M. Bednara, J. Teich.
A new approach for on-line placement on reconfigurable devices, in: 18th International Parallel and Distributed Processing Symposium, 2004., 2004.

[85]

Z. Alliance.
Zigbee specification, ZigBee Alliance, 2005, n^o ZigBee Document 053474r06, Version, Technical report.

[86]

V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.
PACT XPP — A Self-Reconfigurable Data Processing Architecture, in: The Journal of Supercomputing, 2003, vol. 26, n^o 2, p. 167–184.

[87]

C. Bobda.
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[88]

C. Bobda, M. Majer, D. Koch, A. Ahmadinia, J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices, in: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, Lecture Notes in Computer Science (LNCS), Springer, August 2004, vol. 3203, p. 1032–1036.

[89]

D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.

[90]

K. Compton, S. Hauck.
Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, n^o 2, p. 171–210
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[91]

G. Constantinides, P. Cheung, W. Luk.
Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, n^o 10, p. 1432- 1442.

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K. Danne, R. Muhlenbernd, M. Platzner.
Executing hardware tasks on dynamically reconfigurable devices under real-time conditions, in: International Conference on Field Programmable Logic and Applications, Lecture Notes in Computer Science, 2006.

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R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.

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A. Dejonghe, B. Bougard, S. Pollin, J. Craninckx, A. Bourdoux, L. Van Der Perre, F. Catthoor.
Green Reconfigurable Radio Systems, in: Signal Processing Magazine, IEEE, 2007, vol. 24, n^o 3, p. 90–101.

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A. Dunkels, B. Gronvall, T. Voigt.
Contiki-a lightweight and flexible operating system for tiny networked sensors, in: Proceedings of the First IEEE Workshop on Embedded Networked Sensors, 2004.

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C. Ebeling, D. Cronquist, P. Franklin.
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A. M. Fahim.
Clock Generators for SOC Processors: Circuits and Architectures (Text, Speech & Language Technology), Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2005.

[98]

R. Hartenstein.
A Decade of Reconfigurable Computing: A Visionary retrospective, in: Design Automation and Test in Europe (DATE 01), Munich, Germany, March 2001.

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R. Hartenstein, M. Herz, T. Hoffman, U. Nageldinger.
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W. Killmann, W. Schindler.
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K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, September 2000, vol. 47, n^o 9, p. 840-848.

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P. L'Ecuyer, R. Simard.
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M. Lee, H. Signh, G. Lu, N. Bagherzadeh, F. Kurdahi.
Design and Implementation of the MorphoSys Reconfigurable Computing Processor, in: Journal of VLSI and Signal Processing-Systems for Signal, Image and Video Applications, March 2000, vol. 24, n^o 2, p. 147–164.

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T. Marescaux, V. Nollet, J. Mignolet, A. Bartica, W. Moffata, P. Avasarea, P. Coenea, D. Verkest, S. Vernalde, R. Lauwereins.
Run-time support for heterogeneous multitasking on reconfigurable SoCs, in: the VLSI journal, 2004, vol. 38, p. 107–130
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G. Marsaglia.
Diehard: A Battery of Tests of Randomness, Florida State University, Tallahassee, FL, USA, 1996
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[107]

D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: International Conference on Compilers, Architectures and Synthesis for Embedded Systems 2002 (CASES 2002), Grenoble, October 2002.

[108]

D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, n^o 1.

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