Team Arénaire

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Section: Software

FloPoCo: a Floating-Point Core generator for FPGAs

Participants : Florent de Dinechin, Bogdan Pasca.

The purpose of the FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm. FloPoCo is a generator of operators written in C++ and outputting synthesizable VHDL automatically pipelined to an arbitrary frequency.

In 2009, FloPoCo has undergone a complete rewrite that makes automatic pipeline much simpler. Division and square root operators were added. Sylvain Collange, from U. Perpignan, contributed basic operators for Logarithm Number System arithmetic, so FloPoCo is now a strict superset of FPLibrary, which is therefore no longer supported. Non-standard operators developed in 2009 include squarers, sum of squares, Karatsuba multipliers, integer adder trees, table-based constant multipliers and floating-point logarithm. Versions 0.9.3, 0.11, 1.15.0, 1.15.1 and 1.15.2 were released in 2009.

Among the known users of FloPoCo are U.T. Cluj-Napoca, Imperial College, U. Madrid, U. P. Milano, T.U. Muenchen, U. Paderborn, U. Pennsylvania, U. Pernambuco, U. Perpignan, U. Tokyo, and several companies.

Status: stable / Target: any / License: GPL/LGPL / OS: Unix, Linux, Windows / Programming Language: C++ / URL:


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