Team aoste

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities

Section: Other Grants and Activities

Nation-wide collaborations

RNTL platform OpenEmbeDD

Participants : Charles André, Benoît Ferrero, Fadoi Lakhal, Robert de Simone, Yves Sorel.

OpenEmbeDD was a large platform project aimed at connecting several formalisms with model-driven engineering tools, in the embedded domain. Its focus was on the use of model-driven approaches to combine various specification formalisms, analysis and modeling techniques, into an interoperable framework. Partners were: INRIA, CEA-List, Thales, Airbus, France Telecom, CS, LAAS, and VERIMAG. Four INRIA teams were involved (ATLAS, Triskell, Aoste and DaRT).

The project was concluded at mid-year, and the final version of the integrated platform by delivered by then on INRIA's forge. It contains amongst other things our contributions on Marte Time model and CCSL, with its TimeSquare implementation. It also contains model-based translations from OpenEmbeddd metamodel to and from SynDEx , and various connections to Polychrony/SME (from the Espresso EPI) that are also related to our work.

The outcome of this platform are intended to be one of the primary inputs to the large ARTEMIS CESAR project.

RNTL project MeMVaTEx

Participants : Marie-Agnès Peraldi-Frati, Dumitru Potop-Butucaru, Yves Sorel.

The partners of the MeMVaTEx project are: Continental, INRIA, CEA-List, CNRS-UTC, and Sherpa Engineering. The project focuses on developing a design methodology, centered on the requirements, their traceability and their validation. The application domain is the design of complex real-time automotive systems. The methodology is based on the standards EAST-ADL2, AUTOSAR, SYSML and MARTE. The last phase of the project is currently centered on the integration of heterogeneous model and tools for validation and verification of requirements. This phase integrates the Simulink and SynDEx tools in order to provide the validation of requirements and models.

During this year, we have been working on the integration of the SynDEx tool in a timing flow based on EAST_ADL2/Autosar and MARTE. A gateway has been developed that exports temporal informations from the hardware and software models to a SynDEx model. SynDEx is used as a test cases verificator linked to the requirements. We worked also on the MeMVaTEx demonstrator for illustrating the previous results.

We held the project final meeting in September 2009, and presented its results in a journal article [15] , and to the ANR yearly symposium.

ANR RT-Simex

Participants : Frédéric Mallet, Julien Deantoni.

This new project is dedicated to the reverse engineering of analysis traces of simulation and execution back up to the source code, or in our case most likely into the original models in a Marte profile representation. The prime contractor is the Obeo company. We held a mid-year meeting in Sophia-Antipolis.


Participants : Julien Boucaron, Dumitru Potop-Butucaru, Robert de Simone.

HeLP is a recently accepted ANR project, with ST MicroElectronics, Verimag, LEAT, and Docea Power (a SME from Grenoble) as other partners. The project name stands for “High-Level/Low-Power” design and analysis.

There are two main focuses inside the project. The first one deals with the comparison of efficient System-Level modeling, between multiple logical clocks originated from synchronous languages on the one hand, loosely timed and approximate-time simulation schemes of SystemC on the other hand. The second focus goes with the modeling of energy consumption and thermal levels for SoCs, their representation in a model-driven engineering approach, and their interaction with time modeling.

We held the kick-off meeting for this project in December in Grenoble. There are links between this project and the ID/TL-M collaboration with ST Microelectronics.

FUI Lambda

Participants : Charles André, Julien Deantoni, Robert de Simone, Frédéric Mallet.

The Lambda project is headed by Thales, with ST Microelectronics, Airbus, Esterel-EDA, CoFluent, CEA-LIst, and several other partners.

Our contribution in this project remains rather light. We bring expertise to help with the definition of a model transformation between SyncCharts and UML State Diagrams. We then contribute to the combination of SysML and Marte artefacts, in the context of SoC design as well as the SPIRIT IP-Xact standard.


Participants : Dumitru Potop-Butucaru, Yves Sorel.

The Parsec project was accepted within the 2009 FUI for projects, and is scheduled to last from 2010 to 2012. This a large project with The partners of the project are Thales, CEA, Elidiss, INRIA, Systerel, OpenWide, Alstom, and TelecomParisTech. The project aims at defining a framework for the development of distributed real-time embedded systems that are subject to strict certification standards such as DO-178B (for avionics), IEC 61508 (for transportation systems), or ISO/IEC 15408 (the Common Criteria for information technology security evaluation).

The AOSTE team will use its expertise in the modeling and distributed real-time implementation of embedded applications using synchronous formalisms and associated tools. The two main scientific challenges of the project are (1) a better modeling of the distributed implementation architectures, allowing code generation for novel architectures and better code generation for architectures we currently handle, and (2) the modeling and efficient implementation of mode changes, as they are specified in an industrial context.

ARC Triade – Combining models of computation for the design of real-time and embedded applications

Participants : Dumitru Potop-Butucaru, Yves Sorel, Robert de Simone.

The Triade Cooperative Research Action (ARC) is a partnership between the AOSTE, DaRT, and ESPRESSO teams of INRIA. Triade aims at using formal models with structuring programmatic constructs as means to translate programs and descriptions written in formalisms widely used in Embedded System and SoC design, and provide a seamless flow of increasingly time-defined and time-accurate models, so as to progressively obtain the final mapped implementation through provably correct steps from the early description elements.

Triade funded regular meetings with our colleagues from Rennes (ESPRESSO) and Lille (DaRT). Two publications resulted [29] , [28] . We intend a common implementation initiative of these topics.


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