Section: Contracts and Grants with Industry

ID/TL-M project with ST MIcroelectronics

Participants : Charles André, Julien Boucaron, Robert de Simone, Benoît Ferrero, Aamir Mehmood Khan.

ID/TL-M is a project launched as part of the larger nano2012 programme conducted by ST Microlectronics in Rhône-Alpes. Its main goal is to study the potential use of model-driven engineering techniques (MDE) for Electronic System-Level Design (ESL) of Systems-on-Chip (SoC). While SystemC is a de-facto standard in this domain, it suffers a number of lacks. One is the absence of clear formal semantics (unlike Esterel), which largely proscribes high-level synthesis; the second is the absence, at the transaction-level modeling (TLM) level, of a clear associated interface, as an Architecture Description Language (ADL), which could support annotations for extra non-functional properties.

The ongoing standard IP-Xact is a candidate for being such an ADL but, being developed by a consortium of industrial partners with too low-level intents, it does not fit with all our aim perfectly. As a result we studied the specialization of Marte to encompass most existing features of Ip-Xact , while being truly extensible to non-functional properties with genericity. As a by-product, formal semantic definition using our CCSL language and Marte Time model are becoming feasible, with synchronous artefacts borrrowed from Esterel as guidelines.

This year we have provided the specification of translations in both directions between Ip-Xact 1.5 and a proper subset of Marte . Links to formal Models of Computation and Communication (MoCCs) have been drawn, andwe expect to implement them soon to allow interpretation and analysis using our K-Passa tool. Logical time multiclock semantics has also been studied, which resulted in the specification of interpretation amenable to Time-Square . The Papyrus UML modeler by CEA, and Eclipse environments shall be considered to support the forthcoming implementations.

We held two meetings in Grenoble this year. Both partners (INRIA Aoste and STM STG) are members of the recently started ANR project HeLP , which adds the low-power and thermal dimensions to the range of non-functional properties.