Section: New Results
Clock-driven real-time implementation of synchronous specifications
Participants : Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin [ EPI ESPRESSO ] .
One important line of work in our project concerns the model-based mapping of the computations and communications of the functional specification onto corresponding resources of the implementation architecture. This mapping comprises both temporal scheduling and spatial allocation aspects. Therefore, we promote an approach which starts from loosely-timed/asynchronous models and proceeds by refining them to fully synchronized ones, using so-called clock calculus techniques under the architecture constraints.
This year, we provided a modeling framework [28] based on an intermediate representation format, called clocked graphs, for polychronous endochronous specifications, which are the ones that can be safely considered for deterministic distributed real-time implementation using static scheduling techniques. Our formalism allows the specification of both “intrinsic” correctness properties of the specification, such as causality and clock consistency, and “external” correctness properties, such as endochrony, which ensure compatibility with the desired implementation architecture, including both hardware and software aspects. Using this formalism, we define a new method for distributed real-time implementation of synchronous specification, where the move from (endochronous) synchronous specification to realtime scheduled implementation is a seamless sequence of model decorations.
When compared with current state-of-the-art, represented by the AAA/SynDEx methodology, this new approach has the advantage of providing a seamless transformation all the way from specification to implementation models. Our approach also has the advantage of promoting activation conditions (known as clocks) as first class citizens, which is not presently the case for SynDEx, where they can be defined only through structured dataflow constructs (which often results in pessimization of both the specification and the implementation).
