Section: New Results
Virtual Platform modeling
Participants : Charles André, Julien Deantoni, Jean-François Le Tallec, Robert de Simone.
In the context of the PhD thesis of Jean-François Le Tallec, funded under the CIM PACA programme jointly with Scaleo Chip, a local SME company, we studied the system-level representation of full embedded platform at virtual levels. Case studies were provided by former such platforms, but not virtual and lower-level, previously implemented by the industrial partner. Models of a dedicated flash memory controller were realized in several fashions (Verilog VHDL, SystemC, Esterel), and then inserted in prototype platform models. The relevance of specific bus protocols (AMBA mainly), and the difficulties encountered with current proposals for such modeling (Ip-Xact standards, existing environments such as the Synopsys tools available in CIM PACA), were instrumental in the definition of new approaches that use the formalisms of Marte Time model and CCSL, to provide abstract yet precise semantics to the virtual components.
Preliminary results were presented in  , in which systematic connection rules are proposed.