Section: New Results

Interoperability and system-level validation of IP component blocks

Participants : Charles André, Benoît Ferrero, Aamir Mehmood Khan, Frédéric Mallet, Robert de Simone.

In the context of the project Sys2RTL of the CIMPACA platform Conception and of the project ID-TLM in collaboration with ST, we are investigating ways to use UML as a modeling framework for the design and integration of Hardware and Software IPs. For interoperability of IPs, the Spirit Consortium promotes the IP-Xact format. IP-Xact only captures the interface of IPs and relies on Hardware Description Languages for the description of the behavior: SystemC for TLM descriptions and VHDL/Verilog for RTL descriptions. To build a virtual platform for System-On-Chips that allows the early analysis and verification of systems, an abstract specification of the IP behavior is required. We propose to use UML as a graphical front-end to capture both structural and behavioral aspects. The UML Profile for MARTE is used to specify the time aspects and capture non-functional properties. Following a Model-Driven Approach, we have developed transformation models in ATL to transform UML models to IP-Xact specifications back and forth. The transformation requires the annotation of UML/Marte models with IP-Xact specific stereotypes. These stereotypes have been gathered in a UML Profile for IP-Xact. Beyond the transformation of structural elements, we are also considering behavioral and non-functional aspects. The CCSL specification provides a golden model, at the timed communicating process level, and against which implementations at different levels must be checked. As a first step, we have built a library of VHDL observers to validate RTL implementations [24] . We are also building a library of SystemC observers that should be available soon to verify the conformance of implementations at the transaction level.