Section: Software
SynDEx
Participants : Maxence Guesdon, Omar Kermia, Yves Sorel [ correspondant ] , Cécile Stentzel.
SynDEx is a system level CAD software implementing the AAA methodology for rapid prototyping and for optimizing distributed real-time embedded applications. Developed in OCAML it can be downloaded free of charge, under the INRIA copyright, at the url: http://www.syndex.org .
The AAA methodology requires the specification of three main ingredients: an application algorithm, an architectural platform, and real-time features or requirements regarding their combination. Given these, SynDEx will explore the space of possible allocations (distribution and scheduling) from application elements to architecture resources and services to match the real-time requirements, using schedulability analyses and heuristic techniques. It will generate automatically distributed real-time code running on the embedded platform. The last major release of SynDEx (V7) allows the specification of multi-periodic applications.
Application algorithms can be edited graphically as directed acyclic task graphs (DAG) where each edge represent a data dependence between tasks, or they may be obtained by translation from various sources, such as (formal) synchronous reactive programs for example http://www.scicos.org , http://www.irisa.fr/espresso/Polychrony , and UML2/MARTE models http://www.omg.org/technology/documents/profile_catalog.htm .
Architectures are represented as graphical block diagrams composed of programmable (processors) and non-programmable (ASIC, FPGA) computing components, interconnected by communication media (shared memories, links and busses for message passing). In order to deal with heterogeneous architectures it may feature several components of the same kind but with different characteristics.
Two types of non-functional properties can be specified for each task of the algorithm graph. First, a period that does not depend on the hardware architecture. Second, real-time features that depend on the different types of hardware components, ranging amongst execution and data transfer time, memory, etc. . Requirements are generally constraints on deadline equal to period, latency between any pair of tasks in the algorithm graph, dependence between tasks, etc.
Exploration of alternative allocations of the algorithm onto the architecture may be performed manually and/or automatically. The latter possibility is achieved by performing real-time multiprocessor shedulability analyses and optimization heuristics based on the minimization of temporal or resource criteria. For example while satisfying deadlines and latencies constraints they can minimize the total execution time (makespan) of the application onto the given architecture, as well as the amount of memory.
The results of each exploration is visualized as timing diagrams simulating the distributed real-time implementation.
Finally, implementation deployments producing the embedded code use dedicated distributed real-time executives, or general purpose real-time operating systems such as Linux/RTAI or Osek for instance. These executives are deadlock-free, based on off-line scheduling policies. Dedicated executives induce minimal overhead, and are built from processor-dependent executive kernels. Presently, executives kernels are provided for: TMS320C40, PIC18F2680, i80386, MC68332, MPC555, i80C196 and Unix/Linux workstations. Executive kernels for other processors can be ported at reasonable cost following these patterns.
