Inria / Raweb 2009
Presentation of the Team alf

Bibliography

Major publications by the team in recent years

[1]: F. Belletti, S. F. Schifano, R. Tripiccione, F. Bodin, P. Boucaud, J. Micheli, O. Pene, N. Cabibbo, S. de Luca, A. Lonardo, D. Rossetti, P. Vicini, M. Lukyanov, L. Morin, N. Paschedag, H. Simma, V. Morenas, D. Pleiter, F. Rapuano.
Computing for LQCD: ApeNEXT, in: Computing in Science and Engineering, 2006, vol. 8, n^o 1, p. 18–29
http://dx.doi.org/10.1109/MCSE.2006.4.
[2]: F. Bodin, A. Seznec.
Skewed associativity improves performance and enhances predictability, in: IEEE Transactions on Computers, May 1997.
[3]: M. Cornero, R. Costa, R. Fernández Pascual, A. Ornstein, E. Rohou.
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems, in: Conference on HiPEAC, Göteborg, Sweden, P. Stenström, M. Dubois, M. Katevenis, R. Gupta, T. Ungerer (editors), Springer, January 2008, p. 130–144.
[4]: R. Costa, E. Rohou.
Comparing the size of .NET applications with native code, in: 3rd Intl Conference on Hardware/software codesign and system synthesis, Jersey City, NJ, USA, P. Eles, A. Jantsch, R. A. Bergamaschi (editors), ACM, September 2005, p. 99–104.
[5]: D. Hardy, I. Puaut.
WCET analysis of multi-level non-inclusive set-associative instruction caches, in: Proc. of the 29th IEEE Real-Time Systems Symposium, Barcelona, Spain, December 2008.
[6]: T. Lafage, A. Seznec.
Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream, in: In Workload Characterization of Emerging Applications, Kluwer Academic Publishers, 2000, p. 145–163.
[7]: P. Michaud.
Exploiting the Cache Capacity of a Single-chip Multi-core Processor with Execution Migration, in: Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), IEEE Computer Society, January 2004.
[8]: P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis.
A study of thread migration in temperature-constrained multi-cores, in: ACM Transactions on Architecture and Code Optimization, 2007, vol. 4, n^o 2, 9 p.
[9]: P. Michaud, A. Seznec, S. Jourdan.
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors, in: International Journal of Parallel Programming, 2001, vol. 29, n^o 1, p. 35-58.
[10]: E. Rohou, M. Smith.
Dynamically managing processor temperature and power, in: Second Workshop on Feedback-Directed Optimizations, 1999.
[11]: A. Seznec, S. Felix, V. Krishnan, Y. Sazeides.
Design trade-offs on the EV8 branch predictor, in: Proceedings of the 29th International Symposium on Computer Architecture (IEEE-ACM), Anchorage, May 2002.
[12]: A. Seznec, N. Sendrier.
HAVEGE: a user-level software heuristic for generating empirically strong random numbers, in: ACM Transactions on Modeling and Computer Systems, October 2003.
[13]: A. Seznec.
Analysis of the O-GEHL branch predictor, in: Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.
[14]: A. Seznec.
The L-TAGE Branch Predictor, in: Journal of Instruction Level Parallelism, May 2007
http://www.jilp.org/vol9.
[15]: A. Seznec.
Decoupled sectored caches: conciliating low tag implementation cost, in: SIGARCH Comput. Archit. News, 1994, vol. 22, n^o 2, p. 384–393
http://doi.acm.org/10.1145/192007.192072.

Publications of the year

Doctoral Dissertations and Habilitation Theses

[16]: E. Petit.
Partitionnement Automatique d'Applications en Codelets Spéculatifs pour les Systèmes Hétérogènes à Mémoires Distribuées, Université de Rennes I, May 2009, Ph. D. Thesis.

Articles in International Peer-Reviewed Journal

[17]: H. Vandierendonck, A. Seznec.
Fetch Gating Control through Speculative Instruction Window Weighting, in: Transaction on HiPEAC, 2009, vol. 2, p. 128-148.

International Peer-Reviewed Conference/Proceedings

[18]: F. Bodin, S. Matz, M. Wang.
Improving Data Locality on the Cell BE Architecture, in: Proceedings of the 22nd International Workshop on Languages and Compilers for Parallel Computing, 2009.
[19]: J. Dusser, T. Piquet, A. Seznec.
Zero-content augmented caches, in: Proceedings of International Conference on Supercomputing '09, June 2009, p. 46-55.
[20]: G. Grosdidier, C. Eisenbeis, F. Bodin, A. Seznec, R. Bilhaut, G. Le Meur, P. Roudeau, F. Touze, J. Angles D'Auriac, J. Carbonell, D. Becirevic, P. Boucaud, O. Brand-Foissac, P. Pene, D. Barthou, P. Guichon, P. Honore, P. Gallard, L. Rilling.
The PetaQCD project, in: Proceedings of the 17th International Conference on Computing in High Energy and Nuclear Physics (CHEP09), Prague, 03 2009
http://hal.in2p3.fr/in2p3-00380246/en/.
[21]: D. Hardy, T. Piquet, I. Puaut.
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches, in: Proc. of the 30th IEEE Real-Time Systems Symposium, Washington, D.C., USA, December 2009.
[22]: D. Hardy, I. Puaut.
Estimation of cache-related migration delays for multi-core processors with shared instruction caches, in: Proc. of the 17th International Conference on Real-Time and Network Systems (RTNS), Paris, France, October 2009.
[23]: B. Lesage, D. Hardy, I. Puaut.
WCET analysis of multi-level set-associative data caches, in: Proc. of the 9th International Workshop on worst-case execution time analysis, in conjunction with the 14th Euromicro Conference on Real-Time Systems, Dublin, Ireland, July 2009.
[24]: P. Michaud.
Online compression of cache-filtered address traces, in: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, April 2009.
[25]: E. Rohou.
Combining Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems, in: Emerging Uses and Paradigms for Dynamic Binary Translation, Dagstuhl, Germany, B. R. Childers, J. Davidson, K. D. Bosschere, M. L. Soffa (editors), Dagstuhl Seminar Proceedings, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 2009, n^o 08441
http://drops.dagstuhl.de/opus/volltexte/2009/1887.
[26]: A. Suciu, T. Carean, A. Seznec, K. Marton.
Parallel HAVEGE, in: Proceedings of the 8th International Conference on Parallel Processing and Applied Mathematic, Sept 2009.
[27]: G. Svelto, A. Ornstein, E. Rohou.
A Stack-Based Internal Representation for GCC, in: First International Workshop on GCC Research Opportunities (GROW09), in conjunction with HiPEAC 2009, January 2009, p. 37–48.

Books or Proceedings Editing

[28]: I. Puaut (editor)
Real-Time Systems, 2009. ECRTS '09. 21st Euromicro Conference on, July 2009, vol. 5409
http://dx.doi.org/10.1109/ECRTS.2009.1.
[29]: A. Seznec, J. S. Emer, M. F. P. O'Boyle, M. Martonosi, T. Ungerer (editors)
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, Lecture Notes in Computer Science, Springer, 2009, vol. 5409.

Internal Reports

[30]: J. Dusser, A. Seznec.
Decoupled Zero-Compressed Memory, INRIA, 2009, n^o RR-7073
http://hal.inria.fr/inria-00426765/en/, Research Report.
[31]: P. Michaud, Y. Sazeides, A. Seznec.
Proposition for a sequential accelerator in future general-purpose manycore processors, INRIA, 2009, n^o RR-7106
http://hal.inria.fr/inria-00433234/en/, Research Report.
[32]: E. Rohou, A. C. Ornstein, A. E. Özcan, M. Cornero.
Combining Processor Virtualization and Component-Based Engineering in C for Heterogeneous Many-Core Platforms, INRIA, 2009, n^o RR-6933
http://hal.inria.fr/inria-00397823/en/, Research Report.
[33]: A. Seznec.
Towards Phase Change Memory as a Secure Main Memory, INRIA, 2009, n^o RR-7088
http://hal.inria.fr/inria-00430010/en/, Research Report.
[34]: H. Vandierendonck, A. Seznec.
Managing SMT Resource Usage through Speculative Instruction Window Weighting, INRIA, 2009, n^o RR-7103
http://hal.inria.fr/inria-00433081/en/, Research Report.

References in notes

[35]: G. M. Amdahl.
Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities, in: SJCC., 1967, p. 483–485.
[36]: S. Balakrishnan, R. Rajwar, M. Upton, K. Lai.
The Impact of Performance Asymmetry in Emerging Multicore Architectures, in: SIGARCH Comput. Archit. News, 2005, vol. 33, n^o 2, p. 506–517
http://doi.acm.org/10.1145/1080695.1070012.
[37]: D. Burger, T. M. Austin.
The simplescalar tool set, version 2.0, 1997, Technical report.
[38]: R. S. Chappell, J. Stark, S. P. Kim, S. K. Reinhardt, Y. N. Patt.
Simultaneous subordinate microthreading (SSMT), in: ISCA '99: Proceedings of the 26th annual international symposium on Computer architecture, Washington, DC, USA, IEEE Computer Society, 1999, p. 186–195
http://doi.acm.org/10.1145/300979.300995.
[39]: C. Ferdinand, R. Wilhelm.
Efficient and Precise Cache Behavior Prediction for Real-Time Systems, in: Real-Time Syst., 1999, vol. 17, n^o 2-3, p. 131–181
http://dx.doi.org/10.1023/A:1008186323068.
[40]: T. S. Karkhanis, J. E. Smith.
A First-Order Superscalar Processor Model, in: Proceedings of the International Symposium on Computer Architecture, Los Alamitos, CA, USA, IEEE Computer Society, 2004, 338 p
http://doi.ieeecomputersociety.org/10.1109/ISCA.2004.1310786.
[41]: K. Kawaguchi.
Hudson monitors executions of repeated jobs, such as building a software project or jobs run by cron.
http://hudson.dev.java.net/.
[42]: B. Lee, J. Collins, H. Wang, D. Brooks.
CPR : composable performance regression for scalable multiprocessor models, in: Proceedings of the 41st International Symposium on Microarchitecture, 2008.
[43]: Y. Liang, T. Mitra.
Cache modeling in probabilistic execution time analysis, in: DAC '08: Proceedings of the 45th annual conference on Design automation, New York, NY, USA, ACM, 2008, p. 319–324
http://doi.acm.org/10.1145/1391469.1391551.
[44]: T. Lundqvist, P. Stenström.
Timing Anomalies in Dynamically Scheduled Microprocessors, in: RTSS '99: Proceedings of the 20th IEEE Real-Time Systems Symposium, Washington, DC, USA, IEEE Computer Society, 1999.
[45]: T. Sherwood, E. Perelman, G. Hamerly, B. Calder.
Automatically characterizing large scale program behavior, in: In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002, p. 45–57.
[46]: K. Skadron, M. Stan, W. Huang, S. Velusamy.
Temperature-aware microarchitecture, in: Proceedings of the International Symposium on Computer Architecture, 2003.
[47]: J. G. Steffan, C. Colohan, A. Zhai, T. C. Mowry.
The STAMPede approach to thread-level speculation, in: ACM Trans. Comput. Syst., 2005, vol. 23, n^o 3, p. 253–300
http://doi.acm.org/10.1145/1082469.1082471.
[48]: V. Suhendra, T. Mitra.
Exploring locking & partitioning for predictable shared caches on multi-cores, in: DAC '08: Proceedings of the 45th annual conference on Design automation, New York, NY, USA, ACM, 2008, p. 300–303
http://doi.acm.org/10.1145/1391469.1391545.
[49]: D. M. Tullsen, S. Eggers, H. M. Levy.
Simultaneous Multithreading: Maximizing On-Chip Parallelism, in: Proceedings of the 22th Annual International Symposium on Computer Architecture, 1995.
[50]: D. M. Tullsen, S. Eggers, H. M. Levy.
Simultaneous Multithreading: Maximizing On-Chip Parallelism, in: Proceedings of the 22th Annual International Symposium on Computer Architecture, June 1995.
[51]: J. Yan, W. Zhan.
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches, in: Proceedings of Real-Time and Embedded Technology and Applications Symposium, 2008. RTAS '08., 2008, p. 80-89.
[52]: J. Yan, W. Zhang.
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches, in: RTAS'08: Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium, 2008, p. 80–89.
[53]: L. R. Y. Zhan, J. Torrellas.
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors, in: HPCA '98: Proceedings of the 4th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, IEEE Computer Society, 1998, 162 p.

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