Team NeCS

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities

Section: New Results

Energy-aware control for systems on-chip

Participants : C. Canudas-de-Wit [ contact person ] , C. Albea-Sanchez, N. Marchand, D. Simon, S. Durand, Y-B. Zhao.

The NeCS team is involved in the ARAVIS project (see 7.1 at ) : the high level of integration in future chips will lead to heterogeneity in the performance of the various integrated components. It appears that introducing control loops at different levels of these chips will be necessary to be compliant with heterogeneous circuits.

Adaptive Control of the Boost DC-AC Converter

The control of boost DC-AC converters is usually accomplished tracking a reference (sinusoidal) signal. The use of this external signal makes the closed-loop control system to be non-autonomous and thus, making its analysis involved. Here we follow a different approach consisting in the design of a control law in order to stabilize a limit cycle corresponding to the desired oscillatory behavior. In that way, no external signals are needed. In [21] , we have proposed some adaptive control laws for the nonlinear boost inverter in order to cope with unknown RL load, that is, the two parameters: R and L are adapted at the same time. These adaptive controls are accomplished by using some state observers for some of the converter variables even when the state variables are measured. The stability properties are derived by resting to via singular perturbation analysis.

Advanced Control Design for Voltage Scaling Converters

In low-power electronics, achieving a high energy efficiency has great relevance. Nowadays, Global Asynchronous Local Synchronous Systems enables to use a Local Dynamic Voltage Scaling architecture, this technique allows achieving a high energy efficiency. Moreover, Local Dynamic Voltage Scaling can be implemented using different approaches. One of them is Vdd-Hopping technique. Different controllers are designed for a Vdd-Hopping searching a better performance in terms of dissipated energy reduction [22] .

A controller which is principally focused on energy-aware, dealing with maximal current peak constraints is designed. It improves considerably the system efficiency, achieves the desired objective in short time and reduces the current peaks. Stability analysis of the closed-loop system is achieved. This controller is patent pending with the name Energy-Aware Control (ENARC).

Energy aware computing power control

The aim of this work is to achieve a good compromise between computing power and energy consumption. This management is especially difficult for 45nm or 32nm known to be at the limit of the scalability. Therefore automatic control loops are designed in order to make the performance fit the requirement.

A patent is currently pending on the energy control of a single node subject. A second one is in preparation for the multi-node energy control.

QoS control

An application software deployment based on a static and worst case point of view is no longer effective for such heterogeneous chips and more flexible designs must be used. It appears that closed-loop control can be integrated at several hardware and software levels of the chips to provide both adaptivity to the operation conditions and robustness w.r.t. variability.

On top of the nodes power control and computing speed control layers, the outer application layer will include a closed-loop controller of the application quality of service (QoS) under constraints of computing and energy resources availability. This loop uses the scheduling parameters provided by the operating system to regulate the application's QoS. In the context of Aravis the computing speed of each integrated node is assumed to be controllable and is also a possible control actuator used by the application level. A first step will be devising a formal definition of the required control performance and stating cost functions to formally associate the QoS with the usable scheduling parameters.


Logo Inria