Section: New Results
Compilation and Synthesis for Reconfigurable Platform
Pattern-Based Compilation, Synthesis and Configuration Generation
Automatic Synthesis of Optimized Application-Dependent Reconfigurable Systems
This year we have extended the previously developed (see section 5.5 ) UPaK system designed for the automatic selection of application-dependent processor extensions and for the application scheduling on these new architectures. In the context of the project we have considered the architecture model of an ASIP processor with extended instruction sets. Extended instructions implement identified and selected computational patterns and can be executed sequentially or in parallel with the ASIP core processor instructions. This provides ways to trade-off execution time against hardware cost. The processor extensions are composed of heterogeneous cells and registers connected by an interconnection structure with the processor's data-path. The number of registers and the structure of interconnections are application-dependent. Each cell implements one or more patterns selected by the UPaK system. The registers store intermediate results that reduce data transfers between our architecture extension and a processor register file.
Our contribution is twofold. We have defined a complete design flow starting from the C specification and resulting in processor extension generation  and we developed a new scheduling model based on the pattern matching principle using the constraint programming approach  ,  ,  . We have also started work on the pattern generation problem. We have developed a prototype of the new pattern generator. Currently it supports additional constraints such as: the critical path lengths, number of inputs and outputs, etc.. The applied technique allows the selection of maximal sub-patterns of patterns satisfying all imposed architectural constraints. We have continued to work on an optimized synthesis of automatically identified computational patterns in order to synthesize corresponding run-time reconfigurable cells.
Run-time reconfigurable architecture modeling
This year we have continued to work on the modeling problem of the run-time partially reconfigurable architecture in order to optimize the execution time and power consumption of the application. The architecture has been defined in the ROMA ANR project. The architecture is parametric, and is composed of memories, a restricted number of communication switches and run time reconfigurable cells at the functional level. In the context of this project a compilation flow has been defined.
Compilation flow: intermediate representation
The loop optimization is a well-known problem. It has been shown that the polyhedral model provides a convenient abstraction in order to perform some program transformations. Its intuitive geometric interpretation facilitates unimodular transformations such as skewing or projection. Moreover, the polyhedral model allows the execution of different operations such as intersection, difference, etc. on the sets of the geometric forms.
In the context of the ROMA project a new representation has been introduced in order to take the advantages of the polyhedral model and of the HCDG graph. In our new intermediate representation, new guards were added. They are associated with polyhedron expressions that express the validity conditions of all guarded nodes. Thanks to that we know exactly which nodes will be computed in a given polyhedral context (before and after transformation). The extended HCDG graph is constructed after the inter iteration data dependency analysis as described in  . We assume that the analyzed programs contain only FOR loops and that their bounds are defined by linear equations which contain the parameters and the loops indexes. This enhanced HCDG graph is currently generated from C source code using the Gecos environment.