Section: Overall Objectives
Keywords : embedded systems, system-on-chip (system on chip, system on-chip), reconfigurable architectures, specialized accelerators, high-level synthesis, loop parallelization, flexible compilation, low-power consumption, fixed-point arithmetic, mobile communications, sensor networks.
Cairn is a common project with CNRS, University of Rennes 1 (ENSSAT Lannion and IFSIC Rennes) and ENS Cachan-Antenne de Bretagne, and is located on two sites: Rennes and Lannion. The team has been created on January the 1 st, 2008 and is a “reconfiguration” of the former R2D2 research team from Irisa.
The scientific aim of Cairn is to study hardware and software architectures of Reconfigurable System-on-Chip ( rs o c ) , i.e. integrated chips which include reconfigurable blocks whose hardware configuration may be changed before or even during execution.
Reconfigurable systems have been considered by research in computer science and electrical engineering for about twenty years  ,  thanks to the possibilities opened up initially by Field Programmable Gate Arrays ( fpga ) technology and more recently by reconfigurable processors  ,   . In fpga , a particular hardware configuration is obtained by loading a binary stream that is used to shape parameterizable blocks into specific hardware functions. In a reconfigurable processor, coarse-grained logic elements operate on word-size operands and employ reconfigurable operators as computing elements. They are generally tightly coupled with one or more processor cores and act as reconfigurable computing accelerators. Usually, the configuration streams are small enough to ensure run-time – or dynamic – reconfiguration. In a broader sense, hardware reconfiguration may happen not only in a single chip, but in a distributed hardware system, in order to adapt this system to changing conditions. This happens, for example, on a mobile system.
Recent evolutions in technology and modern hardware systems confirm that reconfigurable chips are increasingly used in recent applications or embedded into more general System-on-Chip ( s o c )  . Rapidly changing application standards in fields such as communications and information security ask for frequent modifications of the devices. Software updates may often not be sufficient to keep devices in the market, but hardware redesigns are quite expensive. The need to continuously adapt to changing environments (e.g. cognitive radio) is another incentive to use dynamic reconfiguration at runtime. Finally, with technologies at 65 nm and below, manufacturing problems strongly influence electrical parameters of transistors, and transient errors caused by particles or radiations will also more and more often appear during execution: error detection and correction mechanisms or autonomic self-control can benefit from reconfiguration capabilities.
Standard processors or system-on-chip enable to develop flexible software on fixed hardware. Reconfigurable platform enables to develop flexible software on flexible hardware .
As the density of chips increases  , power efficiency has become "the Graal" of chip architects: not only for portable devices but also for high-performance general-purpose processors, power (or energy) considerations are as important as the overall performance of the products. This power challenge can only be tackled by using application-specific architectures, or at least by incorporating some application-specific elements into s o c s, as asic s (Application Specific Integrated Circuit) are much more power-efficient than gpp s (General-Purpose Processor). The designers of s o c s thus face a very difficult challenge: trading between the flexibility of gpp which leads to high-volume and short design time, and the efficiency of asic s which helps solving the power efficiency problem. Therefore, reconfigurable architectures are often recognized to exhibit the best trade-off potential between power, performance, cost and flexibility  ,  because their hardware structure can be adapted to the application needs.
However, reconfigurable systems raise several questions:
What are the basic elements of a good reconfigurable system? In the early days, they were bit-level operators, and they tend to become word-level operators. There is however no agreement on the model that should be used.
How can we reconfigure such a system quickly? When to reconfigure? What is the information needed to reconfigure?
How can we program efficiently reconfigurable systems? We would like to have compilers, not hardware synthesizers and place-and-routers.
In an application, what must be targeted to reconfigurable chips and what to conventional processors? More generally, how can we transform and optimize an algorithm to take advantage of the potential of reconfigurable chips?
The scientific goal of Cairn is to contribute to answer these questions, based on our background and past experience. To this end, Cairn intends to approach energy efficient reconfigurable architectures from three angles: the invention of new reconfigurable platforms, associated design and compilation tools, and the exploration of the interaction between algorithms and architectures. Power consumption and processing power are considered as the main constraints in our proposed architecture, design flow and algorithm optimizations, in order to maximize the global energy efficiency of the system.
Wireless Communicationis our privileged field of applications. Our research includes the prototyping of parts of these applications on reconfigurable and programmable platforms. Moreover in the framework of research and/or contractual cooperations other application domainsare considered: image indexing, video processing, cryptography and traffic filtering in high-speed networks.
Members of CAIRN team have collaboration with large companies like STmicroelectronics, Thomson, Thales, Atmel, Xilinx, Geensys or SME like Aphycare Technologies, SmartQuantum, R-interface and are involved in several national or international funded projects (ITEA2 Geodes, ANR funded Cifaer, Fosfor, SoCLib, Roma, SVP, Semim@ge, OverSoC, BioWiic and "Poles de compétitivités" funded Spring, Captiv, Transmedi@, RPS2).