Team Cairn

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Bibliography

Major publications by the team in recent years

[1]
L. Collin, O. Berder, P. Rostaing, G. Burel.
Optimal Minimum Distance Based Precoder for MIMO Spatial Multiplexing Systems, in: IEEE Transactions on Signal Processing, March 2004, vol. 52, no 3.
[2]
P. Coussy, E. Casseau, P. Bomel, A. Baganne, E. Martin.
A Formal Method for Hardware IP Design and Integration under I/O and Timing Constraints, in: ACM Transactions on Embedded Computing Systems, 2006, vol. 5, no 1, p. 29-53.
[3]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[4]
S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, Best Paper Award, July 2007, p. 10–18.
[5]
J. Diguet, D. Chillet, O. Sentieys.
A Framework for High Level Estimations of Signal Processing Implementations, in: Journal of VLSI System for Signal, Image and Video Technology, July 2000, vol. 25, no 3.
[6]
K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, no 12-15.
[7]
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, p. 1–15.
[8]
D. Menard, O. Sentieys.
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[9]
C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, 2006, vol. 14, no 6.
[10]
P. Quinton, V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
[11]
C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.

Publications of the year

Doctoral Dissertations and Habilitation Theses

[12]
A. Courtay.
Consommation d'énergie dans les interconnexions sur puce : Estimation de haut niveau et optimisations architecturales, High-Level Estimation and Architectural Optimization of the Interconnection Power Consumption in System-on-Chip , Ph. D. Thesis, University of South Brittany, ENSSAT, November 2008.
[13]
J. Lallet.
MOZAIC: plateforme générique de modélisation et de conception d'architectures reconfigurables dynamiquement, Mozaic: a generic platform for modeling and designing dynamically reconfigurable architectures , Ph. D. Thesis, University of Rennes 1, ENSSAT, November 2008.
[14]
T. Saidi.
Architectures matérielles pour la technologie WCDMA étendue aux systèmes mulit-antennes, Hardware Architectures for WCDMA technology extended to mulitple-antenna systems , Ph. D. Thesis, University of Rennes 1, ENSSAT, July 2008.

Articles in International Peer-Reviewed Journal

[15]
R. Chikhi, S. Derrien, A. Noumsi, P. Quinton.
Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval, in: International Journal of Electronics, July 2008, vol. 95, no 7, p. 621 - 635.
[16]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, no 1, p. 21-33.
[17]
S. Derrien, P. Quinton.
Hardware Acceleration of HMMER on FPGAs, in: Journal of Signal Processing Systems, October 2008, vol. Online http://www.springerlink.com/content/x2618486058j8126/, p. 1-15.
[18]
B. L. Gal, E. Casseau, S. Huet.
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on Very Large Scale Integration Systems, Nov 2008, vol. 16, no 11, p. 1454-1464.
[19]
D. Menard, R. Rocher, O. Sentieys.
Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems, in: IEEE Transactions on Circuits and Systems I: Regular Papers,, November 2008, vol. 55, no 10, p. 1-11.
[20]
D. Menard, R. Serizel, R. Rocher, O. Sentieys.
Accuracy Constraint Determination in Fixed-Point System Design, in: EURASIP Journal on Embedded Systems, 2008, vol. 2008, 12 p.
[21]
S. Pillement, O. Sentieys, R. David.
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), Article ID 562326, 13 pages, 2008, p. 1-13.

Articles in National Peer-Reviewed Journal

[22]
D. Chillet, R. David, E. Grace, O. Sentieys.
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation, in: Technique et Science Informatiques, February 2008, vol. 27, no 1, p. 181 - 202.
[23]
D. Chillet, S. Pillement, O. Sentieys.
Ordonnancement de tâches par réseaux de neurones pour architectures de SoC hétérogènes, in: Traitement du signal, Sélectionné pour Numéro spécial Contributions au colloque Gretsi 2007, 2008.
[24]
B. L. Gal, E. Casseau, C. Andriamisaina.
Synthèse de haut niveau tenant compte de la dynamique des traitements, in: Technique et Science Informatiques, Dec 2008, vol. 27, no 9-10, p. 1129-1154.

International Peer-Reviewed Conference/Proceedings

[25]
G. Adouko, F. Charot, C. Wolinski.
A New Multi Gigabit String Matching Engine, in: International Conference Engineering of Reconfigurable Systems and Algorithms ERSA'08, Las Vegas, USA, July 2008.
[26]
O. Berder, P. Quémerais, O. Sentieys, J. Astier, T. Nguyen, J. Ménard, G. Le Mestre, Y. Le Roux, Y. Kokar, G. Zaharia, R. Benzerga, X. Castel, M. Himdi, G. El Zein, S. Jegou, P. Cosquer, M. Bernard.
Cooperative communications between vehicles and intelligent road signs, in: Proceedings of the 8th International Conference on ITS Telecommunication (ITST), Phuket, Thailand, October 2008.
[27]
F. Charot, C. Wolinski, N. Fau, F. Hamon.
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture, in: 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, Stanford, USA, April 2008.
[28]
F. Charot, C. Wolinski, N. Fau, F. Hamon.
A Parallel and Modular Architecture for 802.16e LDPC Codes, in: 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD'08, Parma, Italy, September 2008, p. 418 - 421.
[29]
D. Chillet, S. Pillement, O. Sentieys.
Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable SoC, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , Bruxelles, Belgium, November 2008.
[30]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
Interconnect Explorer: a High-Level Estimation Tool for On-Chip Interconnects, in: Sophia Antipolis MicroElectronics Forum (SAME 2008), Nice, France, University Booth, October 2008.
[31]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
New directions in interconnect performance optimization, in: International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), Tozeur, Tunisia, March 2008, p. 1-6.
[32]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses, in: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, March 2008.
[33]
E. Grace, R. David, D. Chillet, O. Sentieys.
MOREA : A Memory-Oriented Reconfigurable Embedded Architecture, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , Bruxelles, Belgium, November 2008.
[34]
T. Hilaire, D. Menard, O. Sentieys.
Bit Accurate Roundoff Noise Analysis of Fixed-Point Linear Controllers, in: IEEE International Conference on Computer-Aided Control Systems (CACSD'08), September 2008, p. 607-612.
[35]
J. Lallet, S. Pillement, O. Sentieys.
Efficient Dynamic Reconfiguration for Multi-context Embedded FPGA, in: SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design, New York, NY, USA, ACM, 2008, p. 210-215.
[36]
L. Lepauloux, P. Scalart, C. Marro.
Low distorsion decoupled crosttalk resistant adaptive noise canceller, in: 11th IEEE International Workshop on Acoustic Echo and Noise Control, Seattle, Washington, USA, September 2008.
[37]
T. Nguyen, O. Berder, O. Sentieys.
Efficient space time combination technique for unsynchronized cooperative MISO transmission, in: IEEE 67th Vehicular Technology Conference (VTC Spring 2008), Marina Bay, Singapore, May 2008, p. 629–633.
[38]
T. Nguyen, O. Berder, O. Sentieys.
Impact of transmission synchronization error and cooperative reception techniques on the performance of cooperative MIMO systems, in: Proceedings of IEEE International Conference on Communications (ICC'08), Beijing, China, May 2008, p. 4601–4605.
[39]
H.-N. Nguyen, D. Menard, R. Rocher, O. Sentieys.
Accuracy Constraint Determination in Fixed-Point System Design, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , Bruxelles, Belgium, November 2008.
[40]
S. Pillement, J. Philippe, O. Sentieys.
A New Approach of Coding to Improve Speed and Noise Tolerance of On-Chip Busses, in: International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), Tozeur, Tunisia, March 2008, p. 1-6.
[41]
J. Prevotet, A. Benkhelifa, B. Granado, E. Huck, B. Miramond, F. Verdier, D. Chillet, S. Pillement.
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources, in: International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, December 3-5 2008.
[42]
C. Wolinski, K. Kuchcinski, J. Teich, F. Hannig.
Area and Reconfiguration Time Overhead Minimization for Communication, in: IEEE International Conference on Field Programmable Logic and Applications FPL'08, Heidelberg, Germany, September 2008.
[43]
C. Wolinski, K. Kuchcinski, J. Teich, F. Hannig.
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures, in: 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD'08, Parma, Italy, September 2008, p. 345 - 352.
[44]
C. Wolinski, K. Kuchcinski, J. Teich, F. Hannig.
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures, in: 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, Stanford, USA, April 2008.
[45]
C. Wolinski, K. Kuchcinski.
Automatic Selection of Application-Specific Reconfigurable Processor Extensions, in: IEEE/ACM Design Automation and Test in Europe DATE'08, Munich, Germany, March 10-14, 2008, p. 1214 - 1219.

National Peer-Reviewed Conference/Proceedings

[46]
G. Adouko, F. Charot, C. Wolinski.
Exploitation optimale des circuits reconfigurables FPGA pour la mise en oeuvre d'un moteur de recherche de motifs, in: Symposium en Architecture de machines (SympA '2008 ), Fribourg, Switzerland, February 2008.

Workshops without Proceedings

[47]
A. Courtay, J. Laurent, N. Julien, O. Sentieys.
Modélisation, estimation et optimisation de la consommation des interconnexions dans les SOC, in: Colloque GDR SOC-SIP, Paris, France, June 2008.
[48]
S. Khan, E. Casseau, D. Menard.
SWP for multimedia operator design, in: Colloque GDR SOC-SIP, Paris, France, June 2008.
[49]
J. Lallet, S. Pillement, O. Sentieys.
Mozaïc : plate-Forme de développement pour architectures recon?gurables, in: Colloque GDR SOC-SIP, Paris, France, June 2008.
[50]
K. Martin, F. Charot, C. Wolinski.
Utilisation combinées d'approches statique et dynamique pour la génération d'instructions spécialisées, in: Colloque GDR SOC-SIP, Paris, France, June 2008.
[51]
C. Wolinski, K. Kuchcinski.
Automatic Identification and Selection of Application-Specific Reconfigurable Processor Extensions, in: ArtistDesign Workshop on Design for Adaptivity, Lund, Sweden, May 2008.
[52]
C. Wolinski, K. Kuchcinski.
Graph Constraints for Reconfigurable System Optimization, in: 7th SweConsNet Workshop of the Network for Sweden-based researchers and practitioners of Constraint technology., Göteborg, Sweden, April 2008.

Scientific Books (or Scientific Book chapters)

[53]
S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.
High-Level Synthesis of Loops Using the Polyhedral Model : The MMAlpha Software, in: High-Level Synthesis From Algorithm to Digital Circuit, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, p. 215-230.

Internal Reports

[54]
T. Hilaire, P. Chevrel.
On the compact formulation of the derivation of a transfer matrix with respect to another matrix, Technical report, INRIA, 2008, no RR-6760
http://hal.inria.fr/inria-00345508/fr/.
[55]
T. Hilaire, P. Chevrel, J. Whidborne.
Finite Wordlength Controller Realizations using the Specialized Implicit Form, Technical report, INRIA, 2008, no RR-6759
http://hal.inria.fr/inria-00345490/fr/.

Other Publications

[56]
A. Courtay, O. Sentieys, J. Laurent, N. Julien.
Procédé et dispositif de codage, système électronique et support d'enregistrement associés, Patent Pending, Reference BFF 08P0103/HC, March 2008.

References in notes

[57]
AIS 31: Functionality Classes and Evaluation Methodology for Physical Random Number Generators. Version 1 (25.09.2001) (mandatory if a German IT security certificate is applied for; English translation), Technical report, 2001.
[58]
A. Ahmadinia, C. Bobda, M. Bednara, J. Teich.
A new approach for on-line placement on reconfigurable devices, in: 18th International Parallel and Distributed Processing Symposium, 2004., 2004.
[59]
V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.
PACT XPP — A Self-Reconfigurable Data Processing Architecture, in: The Journal of Supercomputing, 2003, vol. 26, no 2, p. 167–184.
[60]
C. Bobda.
Introduction to Reconfigurable Computing: Architectures Algorithms and Applications, Springer, 2007.
[61]
C. Bobda, M. Majer, D. Koch, A. Ahmadinia, J. Teich.
A Dynamic NoC Approach for Communication in Reconfigurable Devices, in: Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Antwerp, Belgium, Lecture Notes in Computer Science (LNCS), Springer, August 2004, vol. 3203, p. 1032–1036.
[62]
D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks, IJCNN'07, Orlando, FL, August, 12-17 2007.
[63]
K. Compton, S. Hauck.
Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, no 2, p. 171–210.
[64]
G. Constantinides, P. Cheung, W. Luk.
Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, no 10, p. 1432- 1442.
[65]
K. Danne, R. Muhlenbernd, M. Platzner.
Executing hardware tasks on dynamically reconfigurable devices under real-time conditions, in: International Conference on Field Programmable Logic and Applications, Lecture Notes in Computer Science, 2006.
[66]
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
[67]
A. Dejonghe, B. Bougard, S. Pollin, J. Craninckx, A. Bourdoux, L. Van Der Perre, F. Catthoor.
Green Reconfigurable Radio Systems, in: Signal Processing Magazine, IEEE, 2007, vol. 24, no 3, p. 90–101.
[68]
C. Ebeling, D. Cronquist, P. Franklin.
RaPiD - Reconfigurable Pipelined Datapath, in: International Workshop on Field Programmable Logic and Applications, Darmstadt, Lecture notes in Computer Science 1142, September 1996, p. 126–135.
[69]
A. M. Fahim.
Clock Generators for SOC Processors: Circuits and Architectures (Text, Speech & Language Technology), Springer-Verlag New York, Inc. , Secaucus, NJ, USA, 2005.
[70]
P. Feautrier.
Dataflow analysis of array and scalar references, in: International Journal of Parallel Programming, 1991, vol. 20.
[71]
R. Hartenstein.
A Decade of Reconfigurable Computing: A Visionary retrospective, in: Design Automation and Test in Europe (DATE 01), Munich, Germany, March 2001.
[72]
R. Hartenstein, M. Herz, T. Hoffman, U. Nageldinger.
Using The KressArray for Configurable Computing, in: Configurable Computing: Technology and Applications, Proc. SPIE 3526, Bellingham, WA, November 1998, p. 150–161.
[73]
W. Killmann, W. Schindler.
A proposal for: Functionality classes and evaluation methodology for true (physical) random number generators, Technical report, T-Systems debis Systemhaus Information Security Services and Bundesamt für Sicherheit in der Informationstechnik (BSI), 2001.
[74]
S. Kim, W. Sung.
Word-Length Optimization for High Level Synthesis of Digital Signal Processing Systems, in: IEEE Workshop on Signal Processing Systems, Boston, October 1998, p. 142-151.
[75]
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, September 2000, vol. 47, no 9, p. 840-848.
[76]
P. L'Ecuyer, R. Simard.
TestU01: A C library for empirical testing of random number generators, in: ACM Trans. Math. Softw., 2007, vol. 33, no 4, 22 p.
[77]
M. Lee, H. Signh, G. Lu, N. Bagherzadeh, F. Kurdahi.
Design and Implementation of the MorphoSys Reconfigurable Computing Processor, in: Journal of VLSI and Signal Processing-Systems for Signal, Image and Video Applications, March 2000, vol. 24, no 2, p. 147–164.
[78]
T. Marescaux, V. Nollet, J.-Y. Mignolet, A. Bartica, W. Moffata, P. Avasarea, P. Coenea, D. Verkest, S. Vernalde, R. Lauwereins.
Run-time support for heterogeneous multitasking on reconfigurable SoCs, in: the VLSI journal, 2004, vol. 38, p. 107–130.
[79]
G. Marsaglia.
Diehard: A Battery of Tests of Randomness, Technical report, Florida State University , Tallahassee, FL, USA, 1996
http://stat.fsu.edu/pub/diehard/.
[80]
D. Menard, D. Chillet, F. Charot, O. Sentieys.
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: International Conference on Compilers, Architectures and Synthesis for Embedded Systems 2002 (CASES 2002), Grenoble, October 2002.
[81]
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1.
[82]
T. Miyamori, K. Olukotun.
REMARC : Reconfigurable Multimedia Array Coprocessor, in: IEICE Transactions on Information and Systems E82-D, February 1999, p. 389–397.
[83]
W. A. Najjar, W. Bohm, B. A. Draper, J. Hammes, R. Rinker, J. R. Beveridge, M. Chawathe, C. Ross.
High-Level Language Abstraction for Reconfigurable Computing, in: Computer, 2003, vol. 36, no 8, p. 63-69.
[84]
V. Nollet, T. Marescaux, D. Verkest, J.-Y. Mignolet, S. Vernalde.
Operating-system controlled network on chip, in: Proceedings of the 41st annual Conference on Design automation, 2004, p. 256–259.
[85]
Philips.
Silicon Hive, Technical report, Philips Inc. , www.siliconhive.com, 2003.
[86]
J. Rabaey.
Reconfigurable Processing: The Solution to Low-Power Programmable DSP, in: IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1997, vol. 1, p. 275–278.
[87]
A. Rukhin, J. Soto, J. Nechvatal, M. Smid, D. Banks.
A Statistical Test Suite for Random and Pseudorandom Number Generators for Statistical Applications, in: NIST Special Publication in Computer Security, 2001, p. 800-22.
[88]
R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, A. Ivanov.
System-on-chip: reuse and integration, in: Proceedings of the IEEE, 2006, vol. 94, no 6, p. 1050– 1069.
[89]
W. Schindler, W. Killmann.
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications, in: CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, 2003, p. 431–449.
[90]
T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk, P. Cheung.
Reconfigurable computing: architectures and design methods, in: IEE Proc.-Comput. Digit. Tech., March 2005, vol. 152, no 2.
[91]
G. Venkataramani, W. A. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm, J. Hammes.
Automatic compilation to a coarse-grained reconfigurable system-on-chip, in: Trans. on Embedded Computing Systems, 2003, vol. 2, no 4, p. 560–589.
[92]
E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, A. Agarwal.
Baring it all to software: The raw machine, in: IEEE Computer, September 1997, vol. 30, no 9, p. 86–93.
[93]
C. Wolinski, K. Kuchcinski, A. Postola.
UPaK: Abstract Unified Pattern Based Synthesis Kernel for Hardware and Software Systems, in: University Booth, DATE 2007, Nice, France, May 2007.
[94]
Z. A. Ye, N. Shenoy, P. Baneijee.
A C compiler for a processor with a reconfigurable functional unit, in: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field Programmable Gate-Arrays, FPGA '00, New York, NY, USA, ACM Press, 2000, p. 95–100.

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