Section: Scientific Foundations
Intensive Signal Processing
These last few years, our research activities are mainly concerned with data parallel models and compilation techniques. Intensive Signal Processing (ISP) with real time constraints is a particular domain that could benefit from this background. Our project covers the following new trend: a data parallel paradigm for ISP applications. These applications are mostly developed on embedded systems with high performance processing units like DSP or SIMD processors. We focus on multi processor architectures on a single chip (System-on-Chip). To reduce the “time to market”, the DaRT project proposes a high level modeling environment for software and hardware design. This level of abstraction already allows the use of verification techniques before any prototyping (as in the Esterel Studio environment from Esterel Technologies  ). This also permits to automatically produce a mapping and a schedule of the application onto the architecture with code generation (as with the AAA method of SynDEx  ). The DaRT project contributes to this research field by the three following items:
- Co-modeling for HP-SoC design:
We define our own metamodels to specify application, architecture, and (software hardware) association. These metamodels present new characteristics as high level data parallel constructions, iterative dependency expression, data flow and control flow mixing, hierarchical and repetitive application and architecture models. All these metamodels are implemented with EMF. Some of them are represented as UML profiles.
- Model-based optimization and compilation techniques:
We develop automatic transformations of data parallel constructions. They are used to map and to schedule an application on a particular architecture. This architecture is by nature heterogeneous and appropriate techniques used in the high performance community can be adapted. New heuristics to minimize the power consumption are developed. This new objective implies to specify multi criteria optimization techniques to achieve the mapping and the scheduling.
- SoC simulation, verification and synthesis:
The data flow philosophy of our metamodel is particularly well suited to a distributed simulation. Thus, we developped a SystemC based simulation environment at two abstraction levels. CABA (Cycle accurate and bit accurate) for accurate performance estimations (power consumption and execution time), and PVT (system level) for fast simulations of complex HP SIMD systems.
To take care of the architecture model and the mapping of the application on it, we use the SystemC platform to simulate at different levels of abstraction the result of the SoC design. This simulation allows to verify the adequacy of the mapping and the schedule (communication delay, load balancing, memory allocation...). We also support IP (Intellectual Property) integration with different levels of specification.
On the other hand, we have been making significant efforts towards the use of formal validation techniques in order to ensure the correctness of designed systems. For that, we particularly consider the synchronous approach.