Team R2D2

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities

Section: Scientific Foundations

Keywords : high-level synthesis, parallel architecture, IC, design methodology, architecture description language, ASIP, specialized processor, retargetable compilation, flexible compilation, fixed-point arithmetic, data coding, precision.

Modeling, synthesis and compilation for reconfigurable platforms

Dedicated hardware accelerator synthesis

Although the architecture of ICs evolves to increasingly programmable and reconfigurable solutions, future silicon systems will continue to integrate specialized hardware components. The design of such components rests on the use of synthesis techniques.

Today circuits synthesis starts from high-level specifications. The specification of programs carrying out regular computations in the form of recurrence equations allows powerful static analyses and transformations of programs for the derivation of regular architectures [4] .

The base of our research is the polyhedral model, which is well-suited to the expression of the calculation parts applications and which allows the expression and the handling of systems of recurrence equations.

There exist many academic environments prototypes for the automatic synthesis of specialized architectures starting from high-level specification: for example, Diastol, Presage, Hifi, Cathedral, Sade, pei and mma lpha. Tools performing a high-level synthesis from the C language now exist on the market: tools based on SystemC( ) like CoCentric SystemC Compiler ( ) of Synopsys, A|RT Builder of Adelante Technologies/Frontier Design, tools based on C and its extensions as Celoxica DK1 Design Suite ( ) of Celoxica.

Few tools rest on a true parallelization but many research projects explore this approach: Flex( ) and Raw( ) at MIT, Piperench( ) at Carnegie-Mellon, Garp( ) at Berkeley, Pico [60] at HPLabs Palo Alto, Compaan( ) in Leiden.

Among these tools let us cite Alpha [6] and mma lpha, initially developed in the project-team Cosi, evolved from Diastol and constitute today a practical environment for the handling of recurrence equations and the high-level synthesis of dedicated hardware accelerators. We are continuing to make evolve mma lpha. The work is done in close cooperation with the CompSys team (LIP, ENS Lyon).

Processor modeling and flexible compilation

Hardware description languages like VHDL or Verilog are largely used to model and simulate processors, but mainly with the aim to design hardware. The design of SoC requires methodologies and tools for the exploration of the architecture design space. This exploration requires the use of architecture description languages (ADL), adapted to the specification of the SoC architecture models. Very early in the design process, ADL play a role for the validation of SoC architectures, and also for the automatic generation of the software development tools necessary to the software and hardware design of the architecture.

Most of the existing architecture description languages aimed at the specification of processor architecture, privileging either the synthesis, or the generation of compilers, or the generation of simulators. None of the existing languages is really directed towards architectural exploration.

In the category of architecture description languages mainly directed towards processor hardware synthesis, one can quote Mimola, developed at the university of Dortmund, and used to describe target machines in the MSSQ and Record [54] compilers. Mimola is very close to hardware description languages like VHDL or Verilog. A Mimola description can be employed for the synthesis, simulation, and code generation, after extraction of the instruction set.

With regard to the architecture description languages mainly directed towards compilation, one can quote nML, designed at the university of Berlin, ISDL proposed by the MIT, MDES developed at the university of Illinois, Expression developed at the University of California at Irvine.

With regard to the architecture description languages mainly directed towards simulation, one can quote LISA [56] , developed at the university of Aachen. LISA allows the generation of cycle-accurate simulators for DSP processors. Both the structure and the behavior can be modeled.

The existing architecture description languages can also be classified according to the modeling level: behavioral or structural. A language like Mimola is of structural level, languages like nML and ISDL are of behavioral level. LISA, Expression and MDES mixes the two levels of modeling.

There is no standard as regards architecture description languages. The ARMOR language developed in the project-team Cosi, constitutes a practical approach for the modeling of complex architectures. It is suited to architectural exploration and automatic generation of software development tools (compiler, simulator, processor design tools, etc.). .

Floating-point to fixed-point conversion

The efficient implementation of an algorithm on a specialized processor, such as for example a DSP (Digital Signal Processor) or an ASIP (Application Specific Instruction-set Processor), or on a hardware structure, such as an ASIC or a FPGA (Field Programmable Gate Array), requires for reasons related to cost, consumption or silicon area constraints, the use of fixed-point arithmetic, whereas the algorithms are usually specified in floating-point arithmetic. This conversion is a tiresome task and error-prone if it is carried out manually. Indeed, some experiments [45] showed that the time devoted to this conversion step is relatively significant, manual conversion being able to represent up to 30% of the total time necessary to the implementation of the algorithm. Let us note in addition that the time-to-market constraint requires the use of high-level development tools, allowing to automate certain tasks.

The existing methodologies for fixed-point data automatic coding [52] , [62] carry out a transformation from floating-point data representation into a fixed-point representation, without taking into account the architecture of the target processor. However the analysis of the influence of the architecture on the precision of computation and the various phases of the code generation shows the need for taking the architecture features into account and for coupling the coding and code generation processes to obtain an implementation of quality in terms of precision of calculations and execution time.

Data coding optimization must be carried out under precision constraint, and it is thus necessary to determine the signal-to-quantization noise ratio (SQNR) of the application. The SQNR determination methods [50] are generally based on simulation. But within the framework of the data coding optimization these methods use an iterative process leading to high times of optimization. The study of analytical techniques offers new perspectives for the accuracy evaluation.


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