Section: Scientific Foundations

Keywords : reconfigurable architecture, computation grain, low-power consumption, Network-on-chip, sensor network, multiple-valued logic, SoC.

New architectures and technologies

By the end of the decade, IC technology should allow to fabricate billion transistors chips, instead of few tens of millions today as illustrated by the document published by the SIA(http://www.itrs.net/Links/2005ITRS/Home2005.htm ) (Semiconductors Industry Association ). The hardware systems of the future equipments will be miniaturized – one now usually speaks about System-on-Chip (SoC) – while mixing architectures which will be highly heterogeneous and will include dedicated hardware accelerators.

Even if electronic CAD tools and associated design methodologies progressed much during last years, the design of new ICs has not become easier. On the contrary, the gap between the capacities offered by the IC technology and the potential of the current design tools – the famous technology gap , – has never been as large. A rather fundamental change in the way of designing circuits is needed.

This evolution of the technology has an impact on the architectures of manufactured ICs. With the years, a migration is noted: from ASIC towards SoC, and in an immediate future towards reconfigurable programmable platforms.

• ASIC were prevalent between 1980 and 1995, and from now on are only used as particular blocks in more complex heterogeneous systems.

• The first SoCs were designed around 1995. Thanks to the increasing density of chips, a complex SoC usually integrates one or more processor cores (general purpose processor or digital signal processor), memory blocks (RAM, ROM, flash memory, EPROM, etc.), as well as many different interfaces useful for the correct working of the system. They combine hardware and software components. Their design relies on the use of synthesis, place and route tools, and libraries of reusable components.

• In the near future, SoC will evolve to platforms, which are structures of integrated architectures, common to a set of algorithms or applications belonging to the same field of applications. The design tools and methodologies must thus make it possible to design a specialized architectures starting from this basic architecture [59] . The platforms will allow the needs for a broader spectrum of applications to be satisfied, at the price of a reduction of the variety of designed circuits.

Associating flexibility with high-performance and energy efficiency, is a critical issue for embedded applications. This is particularly true for mobile applications. These three constraints are taken into consideration in our architecture studies.

New reconfigurable architectures

These last years saw the emergence of new reconfigurable architectures [47] , which are an alternative to the traditional performance/flexibility compromise, conditioning the choice between purely hardware (ASIC) or purely software (programmable processor) solutions. For an application domain like mobile telecommunications, three main constraints have to be combined: high-performance, low-power consumption and flexibility. Computation grain, reconfiguration schemes, are open research topics.

As an example, the Pleiades [57] project is an architectural platform supporting several computation grains – logic operations are treated as effectively as the arithmetic operations, – designed in order to consume a minimum of energy whatever the level of required performance. However, this platform does not make it possible to support the set of constraints previously discussed because of the static feature of its reconfiguration which limits it to certain field of applications, the coding of words having been the support of the study.

In addition to these two examples, many reconfigurable architectures are based on FPGA-type circuits and the majority of them, such as GARP [49] , NAPA [58] , Chimaera [48] , integrate a traditional programmable processor in charge of the sequencing of the treatments on the reconfigurable block. Other architectures such as Piperench [44] or RaPiD [35] can be reconfigured at a higher level, respectively at the operator and functional level. The concept of computation grain indeed constitutes an interesting and significant research subject. The majority of the FPGA circuits are fine grain since they can be reconfigured at the bit level, which contrasts with programmable processors that manipulate words (32-bit words for a number of them). When bit-level reconfiguration is not required by the application, coarse-grained structures must be built starting from the elementary blocks of the reconfigurable structure, which results in a over-cost of the circuit. To limit this over-cost, new coarse-grained reconfigurable architectures are proposed. This results in structures in which the elementary blocks correspond to arithmetic logic units, multipliers, memories, etc. In addition to Piperench and RaPiD already mentioned, the architectures  Matrix [40] at MIT, MorphoSys [55] at the University of California at Irvine, can be quoted. And among the commercial realizations: the array of reconfigurable arithmetic logic units of Elixent, and the XPP processors of PACT(http://www.pactcorp.com/ ).

Network on Chip design

The rapid growth of device densities on silicon has made it possible to deploy complete systems (SoC) using validated IP blocks. Traditional common interconnection resource is a shared bus. Increasing the number of blocks connected on this bus emphasizes the limitation of this solution. Among those limitations stand the increasing noise sensibility and the scalability of the interconnection scheme. In order to precisely control the electrical and scalability parameters [36] of the interconnect, in-chip communications have to be organized. A new paradigm is rising to face the interconnect issue [34] . The Network on Chip (NoC) concept proposes to use well-defined network layers to build the interconnection scheme. It separates the communication process into three different layers which provide the other layers with services (error detection or correction, routing or packetizing for example). A NoC is dedicated to the reliable and efficient routing of information grouped in packets (with redundancy information, routing information, etc.).

Assuming that the voltage swing on wires will decrease in the next few years, the reliability of the physical layer will decrease. The challenge is to provide a reliable, efficient and low-power link to meet the requirements of future SoCs.

Wireless sensor networks

Wireless sensor networks are groups of sensors interconnected with each other through wireless links. The aim of these sensor networks is to collect information from the area and to relay it through the network. Sensor networks have raise neww challenges in wireless communications [39] . First, the autonomy or the lifetime of a sensor network must be very high, since the sensors can be integrated in concrete, in the soil or even in the body of living beings where the replacement of the batteries is impossible or difficult. Energy-scavenging techniques can be used for that purpose. Then, these networks have to be self-organize since they have to cope with local sensor breakdowns, for example when some sensors run out of power. Another important singularity is the fact that the data rate needed by the applications should be quite low, since the data does not have to be sent continuously, but only when changes occur. Many applications have been proposed, in miscellaneous domains of activities, e.g. in agriculture, building, bridges, transport, military applications, enemy monitoring, chemical and bacteriological monitoring, emergency after earthquakes. Many wireless systems already exist and are commercially successful. Their specifications have generally been developed in order to maximize the spectral efficiency. In sensor networks, the energy is more critical than the available spectrum. For these kind of applications we should rather maximize the power efficiency than the spectral efficiency. A communication system can be described functionally by dividing the processing in layers. The OSI (Open Systems Interconnection) model describes seven layers for the processing. The problem is that the design of a communication system cannot efficiently be done for each layer separately because layers are coupled to each other. Separate optimizations for each layer is not sufficient. That is why designing a power-efficient system must take into account this coupling, by making cross-layer optimizations  [43] . For that reason, it is better to consider few layers.

We worked with a fragmentation of the protocol stack in only two layers. The higher-level part includes the aims of OSI application, presentation, session, transport, and network levels. The lower-level part includes the aims of OSI data-link and physical levels. The lower-level part considers a transmission between two neighbor nodes and has to optimize the communication from this point of view. The higher-level part considers a transmission between generally distant applications, assuming that the lower-level communication used are energy-efficient.

This fragmentation has already been used in [61] , and can be justified by saying that networking issues are coupled together only in the higher-layer part, while the channel management issues are coupled only in the lower-layer part.

Multiple-Valued Logic (MVL) architectures and circuits

Nowadays, numerical systems are exclusively based on a binary representation of numbers and computations. It was shown that the use of a higher number of logical states can reduce the number of interconnection wires and the memory area [41] . It also optimizes the arithmetic processing.

ICs performances are limited by complex wiring –a great amount of the chip performance is devoted to interconnection–, large propagation delay and high-power consumption. Using Multiple-Valued Logic (MVL) techniques, the amount of interconnections and the power consumption caused by important switching activity on each node of a circuit can be reduced. The SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC) is a new promising approach for the implementation of MVL functions in voltage-mode. It combines low-energy consumption and a speed equivalent to binary CMOS structures.