Team R2D2

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities


Major publications by the team in recent years

F. Charot, G. Le Fol, P. Lemonnier, C. Wagner, C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing: the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, no 6.
R. David, D. Chillet, S. Pillement, O. Sentieys.
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, in: SOC Design Methodologies, Kluwer Academic Publishers, 2002, p. 51–62.
R. David.
Architecture reconfigurable dynamiquement pour applications mobiles, Thèse de Doctorat, Université de Rennes, July 2003.
F. Dupont de Dinechin.
Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications, Thèse de doctorat, université de Rennes I, January 1997.
K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, no 12-15.
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse de doctorat, Université de Rennes 1, December 1989.
D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, Thèse de doctorat, Université de Rennes 1, December 2002.
V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, Université de Rennes 1, March 1999.
P. Quinton, V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
P. Quinton, Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.
C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.

Publications of the year

Doctoral dissertations and Habilitation theses

M. Cartron.
Vers une plate-forme efficace en énergie pour les réseaux de capteurs sans fil, Ph.D. Thesis, University of Rennes 1, ENSSAT, December 2006.
E. Kinvi-Boh.
Conception de circuits en logique ternaire : de la caractérisation au niveau transistor à la modélisation architecturale, Ph.D. Thesis, University of Rennes 1, ENSSAT, November 2006.
R. Rocher.
Evaluation analytique de la précision des systèmes en virgule fixe, Ph.D. Thesis, University of Rennes 1, ENSSAT, December 2006.

Articles in refereed journals and book chapters

D. Chillet, R. David, E. Grace, O. Sentieys.
Hiérarchie mémoire reconfigurable: vers une structure de stockage faible consommation, in: Technique et Science Informatiques, to appear, 2007.
L. Kessal, N. Abel, D. Demigny.
Traitement temps réel des images en exploitant la reconfiguration dynamique : architecture et programmation, in: Traitement du Signal, 2006, vol. 23, no 1, p. 41–58.
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, p. 1–15.
R. Rocher, D. Menard, N. Hervé, O. Sentieys.
Fixed-Point Configurable Hardware Components, in: EURASIP Journal on Embedded Systems (JES), 2006, vol. 2006, no 1, Article ID 23197, 13 pages p.

Publications in Conferences and Workshops

N. Abel, L. Kessal, S. Pillement, D. Demigny.
Clear stream towards dynamically reconfigurable systems on chip, in: Workshop ReCoSoC 2006, Reconfigurable Communication-Centric SoCs, Montpellier, France, June 2006.
G. Adouko, F. Charot, S. Gombault, T. Ramard, C. Wolinski.
Panorama des algorithmes efficaces et des architectures matérielles pour le filtrage réseau haut débit et la détection d'intrusion, in: Manifestation des Jeunes Chercheurs STIC (MajecStic), Lorient, November 2006.
C. Andriamisaina, B. Le Gal, E. Casseau.
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems, in: SiPS'06, IEEE 2006 Workshop on Signal Processing Systems, Banff, Canada, October 2006.
C. Andriamisaina, B. Le Gal, E. Casseau.
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems, in: SOCC 2006, IEEE System on Chip Conference, Austin, USA, September 2006.
S. Chevobbe, R. David, F. Blanc, T. Collette, O. Sentieys.
Control unit for parallel embedded system, in: Workshop ReCoSoC 2006, Reconfigurable Communication-Centric SoCs, Montpellier, France, June 2006.
C. T. Djamegni, P. Quinton, S. Rajopadhye, T. Risset.
Une approche itérative pour l'allocation des tâches sur réseaux réguliers, in: Proceedings of the Colloque Africain sur la Recherche en Informatique (CARI'06), Cotonou, Benin, November 2006.
G. Georges, S. Derrien, S. Rubini, F. Raimbault, L. Amsaleg, D. Lavenier.
ReMIX : une architecture pour la recherche dans les masses de données indexées, in: Symposium en Architecture de Machines (Sympa'2006), 2006.
B. Le Gal, E. Casseau.
IP generation targeting multiple bit-width standards, in: ICECS, IEEE International Conference on Electronics, Circuits and Systems, Nice, France, December 2006.
A. Noumsi, S. Derrien, P. Quinton.
Acceleration of a content-based image-retrieval application on the RDISK cluster, in: International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006.
J.-M. Philippe, E. Kinvi-Boh, S. Pillement, O. Sentieys.
An Energy-Efficient Ternary Interconnection Link for Asynchronous Systems, in: ISCAS'06: Proceedings of the International Symposium on Circuits and Systems, IEEE CAS Society, May 2006.
J.-M. Philippe, S. Pillement, O. Sentieys.
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects, in: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, IEEE Computer Society, 2006, p. 334-339.
R. B. Porter, J. R. Frigo, M. Gokhale, C. Wolinski, F. Charot, C. Wagner.
A Programmable, Maximal Throughput Architecture for Local Neighborhood Image Processing, in: Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), Napa, USA, April 2006.
R. B. Porter, J. R. Frigo, M. Gokhale, C. Wolinski, F. Charot, C. Wagner.
A Run-Time Reconfigurable Parametric Architecture for Local Neighborhood Image Processing, in: Proceedings of the Digital System Design Conference (DSD'06), Dubrovnik, Croatia, September 2006.
P. Quinton, T. Risset, K. Morin-Allory, D. Cachera.
Using Mathematica to Design Parallel Programs and Integrated Circuits, in: Proceedings of the 6th International Mathematica Symposium (IMS'06), Avigon, France, June 2006.
R. Rocher, N. Herve, D. Menard, O. Sentieys.
Fixed-point Configurable Hardware Components for Adaptive Filters, in: ISCAS'06: Proceedings of the International Symposium on Circuits and Systems, IEEE CAS Society, May 2006.

References in notes

L. Benini, G. D. Micheli.
Networks on Chips: a New SoC Paradigm, in: IEEE Computer, January 2002, vol. 35, no 1, p. 70–78.
D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.
W. Dally, B. Towles.
Route Packets, Not Wires: on-chip Interconnection Networks, in: Proceedings of the 38th Design Automation Conference, June 2001.
A. Darte, S. Derrien, T. Risset.
Hardware/Software Interface for Multi-Dimensional Processor Arrays, in: IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2005.
A. Darte, R. Schreiber, B. R. Rau, F. Vivien.
Constructing and exploiting linear schedules with prescribed parallelism, in: ACM Trans. Des. Autom. Electron. Syst., 2002, vol. 7, no 1, p. 159–172.
J. J. da Silva, J. Shamberger, J. Ammer, C. Guo, S. Li, R. Shah, T. Tuan, M. Sheets, J. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright.
Design Methodology for PicoRadio Networks, in: Design, Automation and Test in Europe Conference, IEEE/ACM, 2001.
A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, Ph. D. Thesis, MIT, 1996.
G. Epstein.
Multiple-Valued Logic Design: An introduction, Institute of Physics Publishing, Bristol, 1993.
R. Gallager.
Low-density parity-check codes, in: IRE Trans. Inform. Theory, Jan. 1962, vol. 8, p. 21-28.
A. Goldsmith, S. Wicker.
Design Challenges for Energy-Constrained Ad Hoc Wireless Networks, in: IEEE Wireless Communications, August 2002, vol. 9, no 4, p. 8–27.
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, April 2000.
T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, October 1996.
S. Guyetant, M. Giraud, L. L'Hours, S. Derrien, S. Rubini, D. Lavenier, F. Raimbault.
Cluster of Reconfigurable Nodes for Scanning Large Genomic Banks, in: Parallel Computing, 2005, vol. 31, no 1, p. 73–96.
R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.
S. Hauck, T. Fry, M. Hosler, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, June 1997.
H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, June 2001.
K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, December 2000, vol. 19, no 12.
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, September 2000, vol. 47, p. 840-848.
L. L'Hours.
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications, in: Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, S. Vassiliadis, N. Dimopoulos, S. Rajopadhye (editors), IEEE Computer Society, July 2005, p. 127–133.
R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.
S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, June 1999.
J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), June 2000.
C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, November 2001.
R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Technical report, HP Laboratories Palo Alto, October 2001, no HPL-2001-249.
M. Srivastava.
Power-aware Communication Systems, in: Power-aware Design Methodologies, M. Pedram, J. Rabaey (editors), Kluwer Academic Publishers, 2002, chap. 11, p. 297–334.
M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.