Section: Contracts and Grants with Industry
Contract with stm icroelectronics on Register Allocation and Instruction Cache Optimizations
This contract funded by stm icroelectronics finished in December 2005, even if our research continues on this topic. Its objective was the improvement of existing techniques for the optimization of the instruction cache use and for the optimization of the register allocation phase. The study targets ST200 architectures, for which the cec team develops a compiler tool chain. Work on instruction cache optimizations are described in Section 6.4 , studies on register allocation in Sections 6.2 and 6.3 .