Team Compsys

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Scientific Foundations
Software
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Section: Software

Procedure Placement

Participants : Fabrice Rastello, Benoit Boissinot.

Within the collaboration with the cec team at stm icroelectronics, a complete framework of procedure placement for instruction cache optimization have been developed. This tool is decomposed into several parts: first the conflict graph is built from a trace (stm icroelectronics implementation); similarly the affinity graph can also be built from the trace (Fabrice Rastello's implementation); then procedure placement can be performed using graph information (Benoit Boissinot, Fabrice Rastello, and stm icroelectronics implementation); finally the placement can be evaluated using an execution trace or directly on the simulator (stm icroelectronics implementation). All those developments are meant to be open-source. See more details in Section  6.4 .


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