Section: Scientific Foundations
Twenty years ago, the subject of compilation was considered to be mature enough to become an industry, using tools like Lex and Yacc for syntax analysis, and Graham-Glanville code-generator generators. The subject was reactivated by the emergence of parallel systems and the need for automatic parallelizers. The hot topic is now the intermediate phase between syntax analysis and code generation, where one can apply optimizations, particularly those that exploit parallelism, either in an autonomous way or with the help of the programmer. In fact, there is parallelism in all types of digital systems, from supercomputers to PCs to embedded systems.
Compilation consists in a succession of code transformations. These transformations are applied to an intermediate representation that may be very similar to the source code (high-level optimization), or very similar to machine code (assembly code and even register transfer level (RTL) for circuit specification). Almost always, the main constraint is that the meaning (or semantics) of the source program must not be altered. Depending on the context, one may have to express the fact that the degree of parallelism must not exceed the number of available resources (processors, functional units, registers, memories). Finally, the specification of the system may enforce other constraints, like latency, bandwidth, and others. In the case of a complex transformation, one tries to express it as a constrained optimization problem.
For instance, in automatic parallelization, the French community has mainly targeted loop optimization. If the source program obeys a few regularity constraints, one can obtain linear formulations for many of the constraints. In this way, the optimization problem is reduced to a linear program to be solved either over the rationals, or, in few cases, over the integers. These are well-known techniques, based on the theory of convex polyhedra – hence the name polyhedral model that is often affixed to the method. Based on this theory, efficient software tools have been developed. One-dimensional and multi-dimensional scheduling techniques  ,  are an outcome of this research and are ubiquitously used for handling nested loop programs (regular circuit synthesis, process networks for instance).
Extending these methods to embedded systems is difficult because the objective function is complex to express. Performance, for instance, is no longer an objective but a constraint, the goal being to minimize the ``cost'' of the system, which may be a complex mixture of the design, the manufacturing, and the operation costs. For instance, minimizing the silicon area improves the yield and hence decreases the manufacturing cost. Power consumption is an important factor for mobile systems. Computer scientists are used to a paradigm in which the architecture is fixed and the only free variable is the program. The critical problem is thus to extend our optimization methods to handle many more free variables, mostly of a discrete nature.
In parallel with compiler research, the circuit design community has developed its own design procedures. These techniques have as input a structural specification of the target architecture, and use many heavy-weight tools for synthesis, placement, and routing. These tools mainly use sophisticated techniques for boolean optimization and do not consider loops. When trying to raise the level of abstraction, circuit designers have introduced the terms architectural synthesis and behavioral synthesis , but the tools did not follow, due to the above mentioned problems (increasing complexity of the constraints, increasing number of free variables).
Technological advances in digital electronics have motivated the emergence of standards for design specifications and design methodologies. Languages like vhdl , Verilog, and SystemC have been widely accepted. The concepts of off-the-shelf components (intellectual property or ip ) and of platform-based design are gaining importance. However, the problem remains the same: how to transform a manual design process into a compilation process?
The first proposal was to use several tools together. For instance, the hardware-software partitioning problem is handled by architecture explorations, which rely on rough performance estimates, and the degree of automation is low. But since the complexity of systems on chip still increases according to Moore's law, there is a pressing need to improve the design process and to target other architectures, like dsp , or reconfigurable fpga platforms. The next generation of systems on chip will probably mix all the basic blocks of today's technology (dsp , Asic, fpga , network, and a memory hierarchy with many levels). We intend to participate in the design and programming of such platforms.
Our vision of the challenges raised by these new possibilities is the following: one has to understand the technological constraints and the existing tools in order to propose innovative, efficient, and realistic compilation techniques for such systems. Our approach consists in modeling the optimization process as precisely as possible and then in finding powerful techniques to get an optimal solution. Past experience has shown that taking simultaneously all aspects of a problem into account is nearly impossible.
Compsys has four research directions, each of which is a strong point in the project. These directions are clearly not independent. Their interactions are as follows: ``Platform-Independent Code Transformations'' (Section 3.3 ) is on top of ``Optimization for Special Purpose Processors'' (Section 3.2 ) and ``Hardware and Software System Integration'' (Section 3.4 ), since its aim is to propose architecture-independent transformations. ``Federating Polyhedral Tools'' (Section 3.5 ) is transversal because these tools are useful in all other research axes.