Inria
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Raweb 2006
Presentation of the Project Compsys
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Compsys
Compilation and Embedded Computing Systems
2006 Research Team Activity Report
Theme :
COM
Presentation of the Project-Team
- Activity Report in
PDF
or
XML
format
Members
Overall Objectives
Scientific Foundations
Introduction
Optimization for Special Purpose Processors
Platform-Independent Code Transformations
Hardware and Software System Integration
Federating Polyhedral Tools
Software
Introduction
Polylib
Pip
MMAlpha
Syntol
SoCLib
Algorithms on Integer Lattices and Memory Reuse Module: Cl@k+Bee
CLooG: Loop Generation
Register Allocation
Procedure Placement
Modification of the UGH Scheduler
New Results
Introduction
Optimized Coalescing for Out-of-ssa Conversion
Register Allocation and ssa Form Properties
Instruction Cache Optimization
On-Chip Traffic Analysis
Loop Transformations for High Level Synthesis
Memory Reuse and Modular Mappings
Modular Scheduling
Scheduling for Synthesis
Optimization for Low Power
Contracts and Grants with Industry
Contract with stmicroelectronics on Register Allocation and Instruction Cache Optimizations
Minalogic SCEPTRE project with stmicroelectronics on SSA, Register Allocation, and JIT Compilation
Minalogic Open-TLM project
Other Grants and Activities
ITEA Project
CNRS Convention with the University of Illinois at Urbana-Champaign (USA)
Inria Support for Collaboration with Federal University, Rio Grande Do Sul (Brasil)
Informal Cooperations
Dissemination
Introduction
Conferences and Journals
Teaching and Thesis Advising
Teaching Responsibilities
Animation
Defense Committees
Workshops, Seminars, and Invited Talks
Bibliography
Publications of the year
References in notes
