Team Compsys

Members
Overall Objectives
Scientific Foundations
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Bibliography

Publications of the year

Articles in refereed journals and book chapters

[1]
P. Feautrier.
Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, p. 459–487.
[2]
P. Feautrier.
Les Compilateurs, in: Encyclopédie de l'Informatique, J.-E. Pin (editor), to appear, Vuibert, 2007.
[3]
A. Fraboulet, T. Risset.
Master Interface for On-Chip Hardware Accelerator Burst Communications, in: Journal of VLSI Signal Processing, to appear, 2007.
[4]
A. Scherrer, N. Larrieu, P. Borgnat, P. Owezarski, P. Abry.
Non Gaussian and Long Memory Statistical Characterisations for Internet Traffic with Anomalies, in: IEEE Transactions on Dependable and Secure Computing (TDSC), to appear, 2007
http://perso.ens-lyon.fr/antoine.scherrer/scherrer-tdsc.pdf.

Publications in Conferences and Workshops

[5]
P. Amiranoff, A. Cohen, P. Feautrier.
Beyond Iteration Vectors: Instancewise Relational Abstract Domains, in: Static Analysis Symposium (SAS'06), Seoul, Corea, August 2006.
[6]
P. Borgnat, N. Larrieu, P. Owezarski, P. Abry, J. Aussibal, L. Gallon, G. Dewaele, N. Nobelis, L. Bernaille, A. Scherrer, Y. Zhang, Y. Labit.
Détection d'attaques de dénis de service par un modèle non gaussien multirésolution, in: Colloque francophone sur l'ingénierie des protocoles (CFIP), Tozeur, Tunisie, November 2006.
[7]
F. Bouchez, A. Darte, C. Guillon, F. Rastello.
Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove?, in: 5th Annual Workshop in Duplicating, Deconstructing, and Debunking (WDDD'06), held in conjunction with the 33rd International Symposium on Computer Architecture (ISCA-33), Boston, USA, July 2006.
[8]
F. Bouchez, A. Darte, C. Guillon, F. Rastello.
Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How, in: 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC'06), New Orleans, USA, November 2006.
[9]
F. Bouchez, A. Darte, F. Rastello.
On the Complexity of Register Coalescing, in: International Symposium on Code Generation and Optimization (CGO'07), to appear, IEEE Computer Society Press, March 2007.
[10]
G. Chelius, A. Fraboulet, E. Fleury.
Demonstration of Worldsens: A Fast Prototyping and Performance Evaluation Tool for Wireless Sensor Network Applications & Protocols, in: Second International Workshop on Multi-hop Ad Hoc Networks: From Theory to Reality (REALMAN), Firenze, Italia, ACM, May 2006, p. 131 – 133.
[11]
G. Chelius, A. Fraboulet, E. Fleury.
Worldsens: A Fast and Accurate Development Framework for Sensor Network Applications, in: The 22nd Annual ACM Symposium on Applied Computing (SAC 2007), Seoul, Korea, to appear, ACM, March 2007.
[12]
H. Cherroun, A. Darte, P. Feautrier.
Scheduling under Resource Constraints using Dis-Equalities, in: Design Automation and Test Europe (DATE'06), March 2006.
[13]
A. Fraboulet, G. Chelius, E. Fleury.
WorldSens: System Tools for Embedded Sensor Networks, in: Real-Time Systems Symposium (RTSS 2006) (Work in Progress), Rio de Janeiro, Brasil, IEEE, December 2006.
[14]
P. Grosse, Y. Durand, P. Feautrier.
Power Modelling of a NoC Based Design for High-Speed Telecommunication Systems, in: 16th PATMOS Workshop - International Workshop on Power And Timing Modeling, Optimization and Simulation, Montpellier, France, September 2006.
[15]
S. Rus, G. He, C. Alias, L. Rauchwerger.
Region Array SSA, in: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT'06), Seattle, WA, USA, September 2006.
[16]
A. Scherrer, A. Fraboulet, T. Risset.
A Generic Multi-Phase On-Chip Traffic Generation Environment, in: IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP'06), Steamboat Springs, Colorado, USA, September 2006.
[17]
A. Scherrer, A. Fraboulet, T. Risset.
Automatic Phase Detection for Stochastic On-Chip Traffic Generation, in: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), seoul, South Corea, ACM Press, October 2006, p. 88 – 93.
[18]
A. Scherrer, N. Larrieu, P. Borgnat, P. Owezarski, P. Abry.
Non Gaussian and Long Memory Statistical Modeling of Internet Traffic, in: 4th International Workshop on Internet Performance, Simulation, Monitoring and Measurement (IPS MOME), Salzbourg, Austria, March 2006.
[19]
A. Scherrer, N. Larrieu, P. Borgnat, P. Owezarski, P. Abry.
Une caractérisation non gaussienne et longue mémoire du trafic Internet et de ses anomalies, in: 5th Conference on Security and Network Architectures (SAR), Seignosse, France, June 2006.

Internal Reports

[20]
F. Bouchez, A. Darte, F. Rastello.
On the Complexity of Register Coalescing, Technical report, LIP, ENS-Lyon, France, March 2006, no RR2006-15
http://www.ens-lyon.fr/LIP/Pub/rr2006.php.
[21]
F. Bouchez, A. Darte, F. Rastello.
Register Allocation: What does Chaitin's NP-Completeness Proof really Prove?, Technical report, LIP, ENS-Lyon, France, March 2006, no RR2006-13
http://www.ens-lyon.fr/LIP/Pub/rr2006.php.
[22]
N. Fournel, A. Fraboulet, P. Feautrier.
Booting and Porting Linux and uClinux on a New Platform, Technical report, ENSL/LIP, February 2006, no RR2006-08.
[23]
N. Fournel, A. Fraboulet, P. Feautrier.
Porting the Mutek Operating System to ARM Platforms, 34 pages, LIP, ENS-Lyon, February 2006, no 2006-12.

Miscellaneous

[24]
G. Chelius, A. Fraboulet, E. Fleury.
WSNet: A Modular Event-Driven Wireless Network Simulator, IDDN 06-370013-000, 2006
http://www.worldsens.net.
[25]
A. Fraboulet, G. Chelius, E. Fleury.
WSim: A Hardware Platform Simulator, IDDN 06-370012-000, 2006
http://www.worldsens.net.

References in notes

[26]
C. Bastoul, P. Feautrier.
Adjusting a Program Transformation for Legality, in: Parallel Processing Letters, March-June 2005, vol. 15, no 1-2, p. 3-17.
[27]
L. A. Belady.
A study of replacement algorithms for a virtual storage computer, in: IBM Systems Journal, 1966, vol. 5, no 2, p. 78–101.
[28]
Z. Budimlić, K. D. Cooper, T. J. Harvey, K. Kennedy, T. S. Oberg, S. W. Reeves.
Fast Copy Coalescing and Live-Range Identification, in: PLDI '02: Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation, New York, NY, USA, ACM Press, 2002, p. 25–32.
[29]
A. Darte, B. R. Rau, R. Schreiber.
Programmatic Iteration Scheduling for Parallel Processors, August 2002, US patent number 6438747.
[30]
A. Darte, R. Schreiber.
Programmatic Method For Reducing Cost Of Control In Parallel Processes, April 2002, US patent number 6374403.
[31]
A. Darte, R. Schreiber, G. Villard.
Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, Special Issue: Tribute to B. Ramakrishna (Bob) Rau, October 2005, vol. 54, no 10, p. 1242-1257.
[32]
E. De Greef, F. Catthoor, H. De Man.
Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications, in: Parallel Computing, 1997, vol. 23, p. 1811-1837.
[33]
E. F. Deprettere, E. Rijpkema, P. Lieverse, B. Kienhuis.
Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures, in: 8th International Workshop on Hardware/Software Codesign (CODES'2000), San Diego, CA, May 2000.
[34]
H. Devos, K. Beyls, M. Christiaens, J. Van Campenhout, D. Stroobandt.
From Loop Transformation to Hardware Generation, in: Proceedings of the 17th ProRISC Workshop, Veldhoven, 11 2006, p. 249-255.
[35]
Benoît. Dupont de Dinechin, C. Monat, F. Rastello.
Parallel Execution of the Saturated Reductions, in: Workshop on Signal Processing Systems (SIPS 2001), IEEE Computer Society Press, 2001, p. 373-384.
[36]
M. Farach-Colton, V. Liberatore.
On Local Register Allocation, in: Journal of Algorithms, 2000, vol. 37, no 1, p. 37-65.
[37]
P. Feautrier.
Parametric Integer Programming, in: RAIRO Recherche Opérationnelle, September 1988, vol. 22, p. 243–268.
[38]
P. Feautrier.
Some Efficient Solutions to the Affine Scheduling Problem, Part I, One Dimensional Time, in: International Journal of Parallel Programming, October 1992, vol. 21, no 5, p. 313-348.
[39]
P. Feautrier.
Some Efficient Solutions to the Affine Scheduling Problem, Part II, Multidimensional Time, in: International Journal of Parallel Programming, December 1992, vol. 21, no 6.
[40]
A. Fraboulet, K. Godary, A. Mignotte.
Loop Fusion for Memory Space Optimization, in: IEEE International Symposium on System Synthesis, Montréal, Canada, IEEE Press, October 2001, p. 95–100.
[41]
C. Guillon, F. Rastello, T. Bidault, F. Bouchez.
Procedure Placement using Temporal-Ordering Information: Dealing with Code Size Expansion, in: Journal of Embedded Computing, 2005, vol. 1, no 4, p. 437-459.
[42]
R. Johnson, M. Schlansker.
Analysis of Predicated Code, in: Micro-29, International Workshop on Microprogramming and Microarchitecture, 1996.
[43]
G. Kahn.
The Semantics of a Simple Language for Parallel Programming, in: IFIP'74, N. Holland (editor), 1974, p. 471-475.
[44]
V. Lefebvre, P. Feautrier.
Automatic Storage Management for Parallel Programs, in: Parallel Computing, 1998, vol. 24, p. 649-671.
[45]
F. Quilleré, S. Rajopadhye, D. Wilde.
Generation of Efficient Nested Loops from Polyhedra, in: International Journal of Parallel Programming, 2000, vol. 28, no 5, p. 469–498.
[46]
F. Quilleré, S. Rajopadhye.
Optimizing Memory Usage in the Polyhedral Model, in: ACM Transactions on Programming Languages and Systems, 2000, vol. 22, no 5, p. 773-815.
[47]
F. Rastello, F. De Ferrière, C. Guillon.
Optimizing Translation Out of SSA using Renaming Constraints, in: International Symposium on Code Generation and Optimization (CGO'04), IEEE Computer Society Press, March 2004, p. 265-278.
[48]
V. C. Sreedhar, R. D.-C. Ju, D. M. Gillies, V. Santhanam.
Translating Out of Static Single Assignment Form, in: Static Analysis Symposium, A. Cortesi, G. Filé (editors), Lecture Notes in Computer Science, Springer, 1999, vol. 1694, p. 194–210.
[49]
V. Sreedhar, R. Ju, D. Gillies, V. Santhanam.
Translating Out of Static Single Assignment Form, in: Static Analysis Symposium, Italy, 1999, p. 194 – 204.
[50]
A. Stoutchinin, F. De Ferrière.
Efficient Static Single Assignment Form for Predication, in: International Symposium on Microarchitecture, ACM SIGMICRO and IEEE Computer Society TC-MICRO, 2001.
[51]
D. Wilde.
A Library for Doing Polyhedral Operations, Technical report, Irisa, Rennes, France, 1993, no 785
http://hal.inria.fr/inria-00074515.

previous
next