## Section: New Results

Keywords : ASIC, FPGA, circuit generator, fixed-point, floating-point, LNS, arithmetic operators, function evaluation, integrated circuit, digit-recurrence algorithms, division, square-root, exponential, logarithm, trigonometric, sine, cosine, tridiagonal systems.

### Hardware Arithmetic Operators

Participants : J. Detrey, F. de Dinechin, R. Michard, J.-M. Muller, N. Veyrat-Charvillon.

#### Digit-recurrence algorithms

In collaboration with Miloš Ercegovac (University of California at Los Angeles), we have improved our digit-recurrence algorithm for evaluating complex square-roots [21] . We have also adapted Ercegovac's E-method to the digit-recurrence solution of some tridiagonal linear systems [40] .

#### Hardware operators for power computation

In collaboration with Arnaud Tisserand, former team member now at
LIRMM, we have worked on new identities to compute power operations
with fixed integer exponent (x^{3}, x^{4}, ... ) in unsigned radix-2
fixed-point or integer representations. The proposed method reduces
the number of partial products using simplifications based on new
identities and transformations. These simplifications are performed
both at the logical and the arithmetic levels. The proposed method
has been implemented in a VHDL generator that produces synthesizable
descriptions of optimized operators. The results of our method have
been demonstrated on FPGA circuits [43] .

#### A new method to compute hardware function evaluation operators

A new method to optimize hardware operators for the evaluation of fixed-point unary functions has been developed with Arnaud Tisserand [44] . Starting from an ideal minimax polynomial approximation of the function, it first looks for a polynomial whose coefficients are fixed-point numbers of small size. It then bounds accurately the evaluation error using the Gappa tool.

#### Floating-point and LNS operators

We have demonstrated the use of FPLibrary as an unbiased comparison tool [19] to select the number representation (between floating-point and logarithmic number system) which leads to the best implementation for a given application [32] . Then, S. Collange (ENS-Lyon student), under the supervision of M. Arnold at Lehigh University, has designed more accurate LNS operators using a cotransformation-based subtraction.

#### Floating-point sine/cosine up to single precision

Parametrized operators for evaluating the sine and cosine functions in floating-point (up to single precision) were developed and integrated in the FPLibrary operator suite [37] . The difficulty of the range reduction for these operators brought us to also develop several alternative solutions, covering the accuracy-performance tradeoff.

#### Floating-point logarithm and exponential up to double precision

An iterative, hardware-oriented algorithms for the evaluation of exponential and logarithm has been designed and implemented by J. Detrey, F. de Dinechin and X. Pujol (ENS-Lyon student) [53] . Compared to the previous table-based approach, it has a longer latency but smaller area. More importantly, the area grows quadratically with the precision of the mantissa, where the previous approach had exponential growth. This allows us to offer double-precision logarithm and exponential operators using only a fraction of the resources of current large FPGAs.