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Section: Software

RdP to VHDL tool

Participant : David Andreu.

The architectural design underlying the SENIS concept leads to embed a complex system within each distributed FES unit (ยง 6.2.1 ); a DSU (Distributed Stimulation Unit) embeds for instance a micro-machine, a RAM manager, reference models, a protocol interpreter, the analogue subsystem and its interface with the digital part. For the design of the digital part of this complex system with a relatively high level of abstraction, we use Petri nets. Its formalism and associated tools ease the description and verification (analysis) phases; we thus designed a tool allowing the implementation to be directly performed from this model. In this purpose, we proposed an approach based on components for the automatic translation into VHDL, of interpreted Petri nets with time. We thus developed a prototype (beta version) allowing this automatic VHDL code generation (producing a VHDL synchronous component) from a graphical description of a Petri net based model.


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