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Section: Software

Keywords : division, circuit, FPGA, ASIC.

Divgen: a Divider Circuit Generator

Participants : R. Michard, A. Tisserand, N. Veyrat-Charvillon.

Divgen is a divider generator. It generates synthesizable VHDL descriptions of division units. Various algorithms, representations, radices, and parameters are supported. Both ASIC and FPGA targets are supported. This generator is developed within a collaboration between Inria and CEA-Léti (see § 6.1 ).

Status: Beta release / Target: ASIC, FPGA / License: GPL / OS: Unix, Linux, Windows (Cygwin) / Programming Language: C++, VHDL / URL: http://lipforge.ens-lyon.fr/projects/divgen


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