Section: New Results
We clearly stated the differences between our algorithm model and the typical model used by the real-time community in the monoprocessor case. We justified that ``release time'' and ``deadline'' are not necessary and that ``strict periodicity'' is sufficient, for applications using signal, image and control processing algorithms. Also, we justified that the ``latency'' constraints is more powerful than ``deadline'' in the sense that on the one hand two deadlines are necessary to impose a latency constraint, and on the other hand these two deadlines over-constraint the system of operations. We proposed a systematic method to transform a problem specified with latency model in a problem specified with deadlines more usual to the real-time community  . We proposed a new model to specify conditionings inside data-flow graph such that its implementation onto distributed architecture is effective, whereas this problem is often neglected leading to dramatic errors observed at run-time. This model was successfully used to develop automatic translator from other languages based on control graphs, such as Scicos and SyncCharts  . Finally, we introduced ``preemption'' in our algorithm model such that it is possible to take into account accurately its cost during off-line scheduling.
We slightly extended our architecture model to take into account program and data memories inside multicomponents. This model is simpler than the hierarchical one described in  but is sufficient to be exploited by the code generator in order to minimize the number of buffers by re-using them with coloured graphs techniques.
We extended the architecture model in order to support the specificities of FPGA: internal memories, configuration of computational units, communication unit with other components (cf. SynDEx-IC section).