Section: New Results
Formal modeling of latency-insensitive systems
The Latency-Insentive approach to GALS design proceeds in several steps: a synchronous ``golden specification'', used as reference, is first de-synchronized into amarked graph (a specific subclass of conflict-free Petri Nets). Then mandatory latencies are introduced at several locations, and the system is re-synchronized in a way compliant with them. Each step requires the introduction of protocol elements needed to control the flow of signal events. In the second stage the virtually infinite (unbounded) Fifo queues introduced in the first stage are replaced by fixed-size so-called Relay-Stations , with both restricted buffering capacities, and also back-pressure wired-in mechanisms. The computation units themselves are surrounded by sequential wrappers, allowing their (gated) clocks to trigger computations only when all signal values have arrived.
We provided the first formal modeling of all these eleements included in the Latency-Insensitive version of de-synchronized systems, and proved their correctness by establishing a number of temporal properties in the ssytem instantiations with a given number of such elements (typically three computation units and several relay-stations). The results were presented at FMGALS, a specialized workshop on Formal Methods for GALS systems  .