Inria / Raweb 2004
Project-Team: DaRT

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Bibliography

Major publications by the team in recent years

[1]
A. Amar, P. Boulet, J.-L. Dekeyser.
Towards Distributed Process Networks with CORBA, in: "Parallel and Distributed Computing Practice on Algorithms", Special Issue on Parallel and Distributed Computing Practice on Algorithms, 2003.
[2]
A. Amar, P. Boulet, J.-L. Dekeyser, F. Theeuwen.
Distributed Process Networks Using Half FIFO Queues in CORBA, in: "ParCo'2003, Dresden, Germany", Parallel Computing, September 2003.
[3]
P. Boulet, A. Cuccurru, J.-L. Dekeyser, C. Dumoulin, P. Marquet, M. Samyn, R. de Simone, G. Siegel, T. Saunier.
MDA for SoC Design: UML To SystemC Experiment, in: "USOC 2004 - International Workshop on UML for SoC Design (Sponsored by DAC 2004), San Diego, California", June 2004.
[4]
P. Boulet, J.-L. Dekeyser, C. Dumoulin, P. Marquet.
MDA for System-on-Chip Design, Intensive Signal Processing Experiment, in: "FDL'03, Fankfurt, Germany", September 2003.
[5]
A. Cuccuru, P. Boulet, J.-L. Dekeyser.
Regular Hardware Architecture Modeling with UML2, in: "FDL04, Lille, France", September 2004.
[6]
N. Kadri, S. .Niar, A. Baba-Ali.
Impact of Code Compression on the Power Consumption in Embedded Systems, in: "international conference on Embedded Systems and Applications ESA'03", June 2003.
[7]
S. Meftali, J. Vennin, J.-L. Dekeyser.
A fast SystemC simulation Methodology fo Multi-Level IP/SoC Design, in: "IFIP International Workshop On IP Based System-on-Chip Design, Grenoble, France", November 2003.
[8]
S. Meftali, J. Vennin, J.-L. Dekeyser.
Automatic Generation of Geographically Distributed System Simulation Models for IP/SoC Design, in: "The 46th IEEE International Symposium on Circuits and Systems, Cairo, Egypt", December 2003.
[9]
S. Niar, L. Eeckhout, K. DeBosschere.
Comparing multiported cache schemes, in: "PDPTA-2003", June 2003.
[10]
H. Sbeyti, S. Niar, L. Eeckhout.
Adaptive Prefetching for Multimedia Applications in Embedded Systems, in: "DATE'04, Paris, France", EDA IEEE, February 2004.

Publications in Conferences and Workshops

[11]
A.-C. Aljundi, J.-L. Dekeyser.
The Effect of the Degree of Multistage Interconnection Networks on their Performance: the Case of Delta and Over-sized Delta Networks, in: "2004 Euromicro on Parallel and Distributed Processing, Coruna, Spain", February 2004.
[12]
A.-C. Aljundi, J.-L. Dekeyser, M.-T. Kechadi.
On the Scalability of Multistage Interconnection Networks, in: "IEEE first International Conference on Information & Communication Technologies: from Theory to Applications, Damascus, Syria", April 2004.
[13]
L. Bondé, C. Dumoulin, J.-L. Dekeyser.
Metamodels and MDA Transformations for Embedded Systems, in: "FDL04, Lille, France", September 2004.
[14]
S. Meftal, J. Vennin, J.-L. Dekeyser.
Méthodologie de simulation multi niveaux, pour la conception de systèmes monopuces en SystemC, in: "CISC04, Jijel, Algeria", sep 2004.
[15]
S. Meftali, J.-L. Dekeyser.
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design, in: "The 4th IEEE International Workshop System-on-Chip for Real-Time Applications (IWSOC 04), Banff, Alberta, Canada", July 2004.
[16]
S. Meftali, J.-L. Dekeyser.
SoC P2P: A Peer-to-Peer IP Based SoCs Design and Simulation Tool, in: "5th IFIP Working Conference on Virtual Enterprises (PRO-VE'04), Toulouse, France", August 2004.
[17]
S. Meftali, M. Samyn, J.-L. Dekeyser.
Approche MDA, avec plateforme SystemC, pour la conception de systèmes monopuces dédiés au traitement de signal intensif, in: "CISC04, Jijel, Algeria", sep 2004.
[18]
M. Samyn, S. Meftali, J.-L. Dekeyser.
Performances Estimation Metamodel for MDA Based SoC Design, in: "International Workshop on IP Based SoC design, Grenoble, France", December 2004.
[19]
M. Samyn, S. Meftali, J.-L. Dekeyser.
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications, in: "FDL04, Lille, France", September 2004.
[20]
E. Turbatu, S. Meftali, S. Niar, J.-L. Dekeyser.
An automatic communication synthesis for high level SoC design using transaction level modeling, in: "FDL04, Lille, France", September 2004.
[21]
J. Vennin, S. Meftali, J.-L. Dekeyser.
Understanding and Extending SystemC User Thread Package to IA-64 Platform, in: "International Workshop on IP Based SoC design, Grenoble, France", December 2004.

Bibliography in notes

[22]
J. Miller, J. Mukerji (editors).
MDA Guide (Draft Version 0.2), 2003,
http://www.omg.org/docs/ab/03-01-03.pdf.
[23]
Object Management Group, Inc. (editor).
MOF 2.0 Core Final Adopted Specification, 2003,
http://www.omg.org/cgi-bin/doc?ptc/03-10-04.
[24]
Object Management Group, Inc. (editor).
U2 Partners' (UML 2.0): Superstructure, 2nd revised submission, January 2003,
http://www.omg.org/cgi-bin/doc?ptc/03-01-02.
[25]
Object Management Group, Inc. (editor).
(UML 2.0): Superstructure Draft Adopted Specification, July 2003,
http://www.omg.org/cgi-bin/doc?ptc/03-07-06.
[26]
M. D. Adams.
The JPEG-2000 Still Image Compression Standard, Technical report, ISO/IEC JTC 1/SC 29/WG 1, September 2001, no N2412.
[27]
R. Allen, K. Kennedy.
Optimizing Compilers for Modern Architectures: A Dependence-based Approach, Morgan Kaufmann Publishers, October 2001,
http://books.elsevier.com/us//mk/us/subindex.asp?maintarget=&isbn=1-55860-286-0&country=United+States&srccode=&ref=&subcode=&head=&pdf=&basiccode=&txtSearch=&SearchField=&operator=&order=&community=mk.
[28]
K. Arnold, J. Gosling, D. Holmes.
The Java Programming Language, 3rd, Addison-Wesley, 2000.
[29]
G. Berry.
Proof, Language and Interaction: Essays in Honour of Robin Milner, MIT Press, 1998, chap. The Foundations of Esterel,
http://www-sop.inria.fr/meije/esterel/doc/main-papers.html.
[30]
OMG. A. Board.
Model Driven Architecture (MDA), Technical report, OMG, 2001, no ormsc/2001-07-01.
[31]
P. Boulet, A. Darte, G.-A. Silber, F. Vivien.
Loop parallelization algorithms: From parallelism extraction to code generation, in: "Parallel Computing", May 1998, vol. 24, no 3-4, p. 421–444.
[32]
P. Boulet, J.-L. Dekeyser, J.-L. Levaire, P. Marquet, J. Soula, A. Demeure.
Visual Data-parallel Programming for Signal Processing Applications, in: "9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy", February 2001, p. 105–112.
[33]
P. Boulet, A. Meena.
The case for Globally Irregular Locally Regular Algorithm Architecture Adequation, in: "Journ es Francophones sur l'Ad quation Algorithme Architecture, Dijon, France", January 2005.
[34]
E. Consortium.
The Eclipse Project, 2003,
http://www.eclipse.org.
[35]
A. Darte, C. Diderich, M. Gengler, F. Vivien.
Scheduling the Computations of a Loop Nest with Respect to a Given Mapping, in: "Lecture Notes in Computer Science", 2001, vol. 1900,
http://link.springer-ny.com/link/service/series/0558/bibs/1900/19000405.htm; http://link.springer-ny.com/link/service/series/0558/papers/1900/19000405.pdf.
[36]
A. Darte, Y. Robert, F. Vivien.
Scheduling and Automatic Parallelization, Birkhauser Boston, 2000,
http://www.springeronline.com/sgw/cda/frontpage/0,11855,5-40109-22-2026983-0,00.html.
[37]
A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J.-C. Dufourd, J.-L. Marro.
Array-OL : Proposition d'un Formalisme Tableau pour le Traitement de Signal Multi-Dimensionnel, in: "Gretsi, Juan-Les-Pins, France", September 1995.
[38]
A. Demeure, Y. Del Gallo.
An Array Approach for Signal Processing Design, in: "Sophia-Antipolis conference on Micro-Electronics (SAME 98), France", October 1998.
[39]
P. Dumont, P. Boulet.
Transformations de code Array-OL : implémentation de la fusion de deux tâches, Technical report, Laboratoire d'Informatique fondamentale de Lille et Thales Communications, October 2003.
[40]
P. Dumont.
Étude des Transformations d'un Code Array-OL dans Gaspard, Research Report, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, France, September 2002, no 02-11,
http://www.lifl.fr/LIFL1/publications/2002-11.ps.
[41]
C. Dumoulin.
ModTransf: A Model to Model Transformation Engine, December 2003,
http://www.lifl.fr/west/modtransf.
[42]
Esterel Technologies.
SoC Design, Validation and Verification, 2002,
http://www.esterel-technologies.com/v3/?id=29453.
[43]
D. D. Gajski, R. Kuhn.
Guest Editor Introduction: New VLSI-Tools, in: "IEEE Computer", December 1983, vol. 16, no 12, p. 11-14.
[44]
T. Gardner, C. Griffin, J. Koehler, R. Hauser.
A Review of OMG MOF 2.0 Query / Views / Transformations Submissions, OMG paper, July 2003,
http://www.omg.org/docs/ad/03-08-02.pdf.
[45]
T. Grandpierre, C. Lavarenne, Y. Sorel.
Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessors, in: "Proceedings of the 7th International Workshop on Hardware/Software Codesign (CODES99), New York", ACM Press, May 3–5 1999, p. 74–78.
[46]
T. Grotker, S. Liao, al.
System Design with SystemC, Kluwer Academic Publishers, 2002.
[47]
M. Gupta, S. Mukhopadhyay, N. Sinha.
Automatic Parallelization of Recursive Procedures, in: "International Journal of Parallel Programming", 2000, vol. 28, no 6, p. 537-562,
http://citeseer.nj.nec.com/gupta99automatic.html.
[48]
N. Halbwachs, J.-C. Fernandez, A. Bouajjanni.
An executable temporal logic to express safety properties and its connection with the language Lustre, in: "Sixth International Symp. on Lucid and Intensional Programming, ISLIP'93, Quebec", April 1993.
[49]
ITRS.
Design, 2001 edition, 2001,
http://public.itrs.net/.
[50]
G. Kahn.
The Semantics of a Simple Language for Parallel Programming, in: "Information Processing 74: Proceedings of the IFIP Congress 74", J. L. Rosenfeld (editor)., North-Holland, IFIP, August 1974, p. 471–475.
[51]
G. Kahn, D. B. MacQueen.
Coroutines and networks of parallel processes, in: "Information Processing 77: Proceedings of the IFIP Congress 77", B. Gilchrist (editor)., North-Holland, 1977, p. 993–998.
[52]
V. Lefebvre, P. Feautrier.
Optimizing Storage Size for Static Control Programs in Automatic Parallelizers, in: "European Conference on Parallel Processing", 1997, p. 356-363,
http://citeseer.nj.nec.com/lefebvre97optimizing.html.
[53]
A. W. Lim.
Improving Parallelism and Data Locality with Affine Partitioning, Ph. D. Thesis, Stanford University, September 2001.
[54]
D. E. Maydan, S. P. Amarasinghe, M. S. Lam.
Array-data flow analysis and its use in array privatization, in: "Conference record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages: papers presented at the symposium, Charleston, South Carolina, January 10–13, 1993, New York, NY, USA", ACM (editor)., ACM Press, 1993, p. 2–15,
http://www.acm.org:80/pubs/citations/proceedings/plan/158511/p2-maydan/.
[55]
M. Mottl.
Automating Functional Program Transformation, Technical report, University of Edinburgh, September 2000,
http://www.ai.univie.ac.at/~markus/msc_thesis/.
[56]
P. K. Murthy, E. A. Lee.
Multidimensional Synchronous Dataflow, in: "IEEE Transactions on Signal Processing", July 2002.
[57]
P. K. Murthy.
Scheduling Techniques for Synchronous and Multidimensional Synchronous Dataflow, Ph. D. Thesis, University of California, Berkeley, CA, 1996.
[58]
OMG.
MOF 2.0 Query / Views / Transformations RFP, OMG paper, 2003,
http://www.omg.org/techprocess/meetings/schedule/MOF_2.0_Query_View_Transf._RFP.html.
[59]
Object Management Group, Inc..
MOF Meta Object Facility, Specification, Version 1.3, January 2000,
http://www.omg.org/cgi-bin/doc?formal/00-04-03.
[60]
Open SystemC Initiative.
SystemC, 2002,
http://www.systemc.org/.
[61]
C. Pareja, R. Peña, F. Rubio, C. Segura.
Optimizing Eden by program transformation, in: "2nd Scottish Functional Programming Workshop, St. Andrews 2000", Intellect, 2001,
http://www.mathematik.uni-marburg.de/~eden/paper/ParejaPenaRubioSeguraSFP2000.ps.
[62]
H. J. Reekie.
Realtime Signal Processing: Dataflow, Visual, and Functional Programming, PhD Thesis, School of Electrical Engineering, University of Technology, Sydney, Australia, September 1995,
http://ptolemy.eecs.berkeley.edu/~johnr/papers/thesis.html.
[63]
M. Serrano, P. Weis.
Bigloo: A Portable and Optimizing Compiler for Strict Functional Languages, in: "Static Analysis Symposium", 1995, p. 366-381,
http://citeseer.nj.nec.com/serrano95bigloo.html.
[64]
Y. Sorel, C. Lavarenne.
SynDEx Documentation Index, INRIA, 2000,
http://www-rocq.inria.fr/syndex/doc/.
[65]
Y. Sorel, C. Lavarenne.
Modèle unifié pour la conception conjointe logiciel-matériel, in: "Traitement du Signal (numéro spécial Adéquation Algorithme Architecture)", 1997, vol. 14, no 6, p. 569-578,
http://www-rocq.inria.fr/syndex/pub.htm.
[66]
Y. Sorel.
Massively Parallel Computing Systems with Real Time Constraints - The ``Algorithm Architecture Adequation'' Methodology, in: "Proceedings of the 1st International Conference on Massively Parallel Computing Systems, Los Alamitos, CA, USA", IEEE Computer Society Press, May 1994, p. 44–54.
[67]
J. Soula.
Principe de Compilation d'un Langage de Traitement de Signal, (In French), Thèse de doctorat (PhD Thesis), Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, December 2001.
[68]
P. Tu, D. Padua.
Chapter 8. Automatic Array Privatization, in: "Lecture Notes in Computer Science", 2001, vol. 1808,
http://link.springer-ny.com/link/service/series/0558/bibs/1808/18080247.htm; http://link.springer-ny.com/link/service/series/0558/papers/1808/18080247.pdf.

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