Project : vertecs
Section: Contracts and Grants with Industry
Agedis [11/2000-01/2004] is an European project IST ( http://www.agedis.de/) on the automated generation and execution of test suites for distributed component based software. The goal of the project is to propose a toolset for test generation, test execution and test result analysis, starting from UML models of distributed software. This project allows us to improve the TGV technology by extending it with coverage based test generation (see 6.2.1) using a more complete API to the IF simulation tool of VERIMAG. It also gives us a new opportunity to connect our technology to the UML world. Partners are IBM Haifa, IBM Hursley, France Télécom R& D, IntraSoft, Imbus, Oxford University and Vérimag. We are subcontractors of Vérimag in this project.