Project : vertecs
Section: New Results
Interaction between test, control and verification
Ensuring the conformance by means of supervisors
The problem addressed here is how to force a known implementation model to conform to a reference specification. The proposed solution is to control the implementation with an internal controller and to compute it by control synthesis techniques, considering conformance with the specification as a control objective. The problem is attacked in the context of total and partial observation of the controller on the implementation  . This work is still under progress.
Robustness is the ability of a system to behave acceptably in the presence of hazards. One problem is the generation of test cases for testing robustness. Given a specification with modes (normal and degraded) and hazards, and required robustness properties, we propose an approach in two phases. First the specification should at least ensure robustness properties, which is achieved by control. Then test cases are selected, focussed on robustness. This is done by using a TGV-like technique on the controlled specification, but focussed on mode changes and hazards, using test purposes derived from properties, and results of the control problem.
Testing and Control of Real-Time Systems
Before visiting us, Ahmed Khoumsi had contributed to the testing and control of real-time systems, based on a transformation of classes of Timed Automata (TA) into equivalent finite state automata called SetExp Automata (SEA). During his visit, we used this transformation as a basis for the generalization of two problems adressed in the project. First, for a class of Determinizable TA, we extended the TGV method to the real-time case . Second, we extended the work on control for conformance for real-time discrete event systems and for a real-time extension of the ioco conformance relation.
Combining Formal Verification and Conformance Testing
Participant : Vlad Rusu.
This work  presents yet another combination of verification and conformance testing techniques to support the formal validation of reactive systems. The idea is to use symbolic test selection techniques to extract subgraphs (components) from a specification, and to perform the verification on the components rather than on the whole specification. Under reasonable sufficient conditions, this constitutes a sound compositional verification technique, in the sense that a property verified on the components also holds on the whole specification. This may considerably reduce the global verification effort. Moreover, once verified, a component forms the basis of an adequate test case, i.e., when executed on an implementation, it will not issue false positive or negative verdicts with respect to the verified properties. The approach has been implemented using the STG test selection tool STG and the PVS theorem prover, and demonstrated on a smart-card application (an electronic purse system).