Team NeCS

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Section: New Results

Energy-aware control of systems on chip

Energy-aware computing power control

Participants : N. Marchand [contact person] , S. Durand.

Achieving a good tradeoff between computing power and energy consumption is one of the challenges in embedded architectures of the future. This management is especially difficult for 45nm or 32nm known to be at the limit of the scalability, i.e., with a high process variability (see [41] for further details). Automatic control loops have therefore to be designed in order to make the performance fit the requirement in order to minimize the energy loss in a context of highly unknown performance of the chip. The main objective is to dynamically control the computing power and the consumption using the voltage and the frequency according to the requirements of the OS. In this way, a robust control law was developed [73] in order to minimize the high voltage running time with predictive technique, i.e. to minimize the energy consumption. Results are shown on figure 17 where the robustness is illustrated for 10% and 20% of process variability.

Figure 17. Energy controller simulation results
IMG/monocore_disparity

This control was done for one node (i.e. a processor) but in ARAVIS SoC, the chip is composed of several clusters with several nodes each (see figure 18 ). Thus, the energy controller has to manage the voltage level (one voltage domain by cluster) and the frequency for all nodes: a maximal frequency is performed for critical node and then a ratio of this frequency could be apply to the other nodes. Thus, a multicore control strategy with low computational needs was proposed [72] .

Figure 18. ARAVIS SoC architecture
IMG/soc_ARAVIS

Two patents have been deposed: the first one for the monocore energy control [71] and the second one for the multicore energy control [75] .

Video decoding QoS control

Participants : D. Simon [Contact person] , A.-M. Alt.

An application software deployment based on a static and worst case point of view is no longer effective for such heterogeneous chips and more flexible designs must be used. It appears that closed loop control can be integrated at several hardware and software levels of the chips to provide both adaptivity to the operation conditions and robustness w.r.t. variability.

On top of the clusters power control and computing speed control layers, the outer application layer includes a feedback loop to control the application quality of service (QoS) under constraints of computing and energy resources availability. This loop uses the scheduling capabilities provided by the operating system to control the application's execution parameters. In the particular context of a H.264/SVC decoder expected to run on the Aravis , the computing speed of each node is a controllable scheduling parameter, as well as the deadlines assigned to decode every frame. A prototype has been implemented on a stock Linux laptop using the event-based programming model provided by the Sardes team : it shows the effectiveness of the approach where very simple closed-loop controllers allow for saving computing energy while preserving a good video decoding quality [13] .


previous
next

Logo Inria