Section: Contracts and Grants with Industry
Pôle de compétitivité Minalogic/ARAVIS
ARAVIS (Architecture reconfigurable et asynchrone intégrée sur puce) is a project sponsored by the Minalogic Pole, started for 3 years in October 2007 ( http://www.minalogic.com/posters/aravis.pdf ). It will investigate innovative solutions needed by the integration of 32 nano-meter scale future chips. It is headed by STMicroelectronics, the other partners are CEA-Leti, TIMA laboratory and the Sardes and NeCS teams at Inria .