Bibliography

Major publications by the team in recent years

[1]

M. Cartron.
Vers une plate-forme efficace en énergie pour les réseaux de capteurs sans fil, Ph.D. Thesis, University of Rennes 1, ENSSAT, December 2006.

[2]

F. Charot, G. Le Fol, P. Lemonnier, C. Wagner, C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing: the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, n^o 6.

[3]

R. David, D. Chillet, S. Pillement, O. Sentieys.
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, in: SOC Design Methodologies, Kluwer Academic Publishers, 2002, p. 51–62.

[4]

R. David.
Architecture reconfigurable dynamiquement pour applications mobiles, Thèse de Doctorat, Université de Rennes, July 2003.

[5]

K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, n^o 12-15.

[6]

C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse de doctorat, Université de Rennes 1, December 1989.

[7]

D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, n^o 1, p. 1–15.

[8]

D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, Thèse de doctorat, Université de Rennes 1, December 2002.

[9]

V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, Université de Rennes 1, March 1999.

[10]

A. Noumsi, S. Derrien, P. Quinton.
Acceleration of a content-based image-retrieval application on the RDISK cluster, in: 20th International International Parallel and Distributed Processing Symposium (IPDPS 2006), April 2006, p. 25-29.

[11]

P. Quinton, V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.

[12]

P. Quinton, Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.

[13]

R. Rocher, D. Menard, N. Hervé, O. Sentieys.
Fixed-Point Configurable Hardware Components, in: EURASIP Journal on Embedded Systems (JES), 2006, vol. 2006, n^o 1, Article ID 23197, 13 pages p.

[14]

R. Rocher.
Evaluation analytique de la précision des systèmes en virgule fixe, Ph.D. Thesis, University of Rennes 1, ENSSAT, December 2006.

[15]

C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, n^o 4-6.

Publications of the year

Doctoral dissertations and Habilitation theses

[16]

I. Benkermi.
Modèle et algorithme d'ordonnancement pour architectures reconfigurables dynamiquement, Ph.D. Thesis, University of Rennes 1, ENSSAT, IRISA, January 2007.

[17]

N. Hervé.
Contributions à la synthèse d'architecture virgule fixe à largeurs multiples., Ph.D. Thesis, University of Rennes 1, ENSSAT, IRISA, March 2007.

Articles in refereed journals and book chapters

[18]

P. Coussy, E. Casseau, P. Bomel, A. Baganne, E. Martin.
Constrained algorithmic IP design for system-on-chip, in: Integration, the VLSI Journal, issue on Systems-on-Chip: Design and Test, February 2007, vol. 40, n^o 2, p. 94–105.

[19]

T. Hilaire, P. Chevrel, J. Clauzel.
Low parametric sensitivity realization design for FWL implementation of MIMO controllers : Theory and application to the active control of vehicle longitudinal oscillations, in: International Journal of Tomography and Statistics, 2007, vol. 6, p. 128–133.

[20]

T. Hilaire, P. Chevrel, J. Whidborne.
A Unifying Framework for Finite Wordlength Realizations, in: Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, August 2007, vol. 54, n^o 8, p. 1765–1774.

[21]

S. Pillement, R. David.
Architectures reconfigurable faible consommation – réalité ou prospective ?, in: Technique et Science Informatiques, numéro spécial SoC, 2007, vol. 26, p. 595–622.

Publications in Conferences and Workshops

[22]

C. Andriamisaina, E. Casseau, P. Coussy.
Synthesis of Multimode digital signal processing systems, in: NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, Scotland, August 2007, p. 318–325.

[23]

E. Casseau, S. Khan, B. Le Gal, W. Aubry.
Multimode architecture design, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 2007.

[24]

C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E. Juin, P. Urard, E. Martin.
A design flow dedicated to multi-mode architectures for DSP applications, in: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 2007, p. 604–611.

[25]

R. Chikhi, S. Derrien, A. Noumsi, P. Quinton.
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC 2007), Mangaratiba, Brazil, P. Diniz, E. Marques, K. Bertels, M. Fernandes, J. Cardoso (editors), Lecture Notes in Computer Science (LNCS), Springer-Verlag, March 2007, vol. 4419, p. 247–258.

[26]

D. Chillet, I. Benkermi, S. Pillement, O. Sentieys.
Hardware Task Scheduling for Heteregeneous SoC Architectures, in: 15th European Signal Processing Conference (EUSIPCO), Poznan, Poland, September 2007, p. 1653–1657.

[27]

D. Chillet, S. Pillement, O. Sentieys.
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures, in: IEEE International Joint Conference on Neural Networks (IJCNN'07), Orlando, FL, USA, August, 12-17 2007, p. 102 – 107.

[28]

D. Chillet, S. Pillement, O. Sentieys.
Vers une implémentation matérielle d'un réseau de neurones pour le service d'ordonnancement des tâches au sein d'un SoC, in: Actes du GRETSI, Troyes, France, September 2007, p. 353–356.

[29]

S. Derrien, P. Quinton.
Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, Best Paper Award, July 2007, p. 10–18.

[30]

M. Djendi, A. Gilloire, P. Scalart.
New frequency domain post-filters for noise cancellation using two closely spaced microphones, in: 15th European Signal Processing Conference (EUSIPCO), Poznan, Poland, September 2007, p. 218–221.

[31]

N. Hervé, D. Ménard, O. Sentieys.
About the importance of operation grouping procedures for multiple word-length architecture optimizations, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC 2007), Mangaratiba, Brazil, P. Diniz, E. Marques, K. Bertels, M. Fernandes, J. Cardoso (editors), Lecture Notes in Computer Science (LNCS), Springer-Verlag, March 2007, vol. 4419, p. 191–200.

[32]

T. Hilaire, P. Chevrel, J. Whidborne.
Low Parametric Closed-Loop Sensitivity Realizations using Fixed-Point and Floating-Point Arithmetic, in: Proc. European Control Conference (ECC), July 2007.

[33]

T. Hilaire, D. Menard, O. Sentieys.
Roundoff Noise Analysis of Finite Wordlength Realizations with the Implicit State-Space Framework, in: 15th European Signal Processing Conference (EUSIPCO), Poznan, Pologne, September 2007.

[34]

S. Huet, S. LeNours, O. Pasquier, E. Casseau.
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications, in: Forum on specification and Design Languages (FDL), Barcelona, Spain, September 2007.

[35]

A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys, S. Pillement.
Modeling of Interconnection Networks in Massively Parallel Processor Architectures, in: Proceedings of 20th International Conference on Architecture of Computing Systems, Zurich, Switzerland, Lecture Notes in Computer Science (LNCS), Springer-Verlag, March 2007, vol. 4415, p. 268–282.

[36]

B. Le Gal, L. Bossuet, S. Khan, E. Casseau.
HLS Design Flow for Multimode IP Generation Under Multiple Constraints, in: IEEE Conference on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, December 2007, p. 314–317.

[37]

D. Menard, R. Serizel, R. Rocher, O. Sentieys.
Noise model for Accuracy Constraint Determination in Fixed-Point Systems, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 2007.

[38]

T. Nguyen, O. Berder, O. Sentieys.
Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks, in: Proceedings of IEEE 65th Vehicular Technology Conference (VTC Spring), Dublin, Ireland, April 2007, p. 85–89.

[39]

T. Nguyen, O. Berder, O. Sentieys.
Energy-efficiency optimization for cooperative MIMO schemes in wireless sensor networks, in: IRAMUS Thematic Informational Workshop, Val Thorens, France, January 2007.

[40]

T. Nguyen, O. Berder, O. Sentieys.
Optimisation énergétique des transmissions MIMO coopératives pour les réseaux de capteurs sans fil, in: Actes du GRETSI, Troyes, France, September 2007, p. 301–304.

[41]

R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Analytical accuracy evaluation of Fixed-Point Systems, in: 15th European Signal Processing Conference (EUSIPCO), Poznan, Poland, September 2007.

[42]

R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Evaluation analytique de la précision des systèmes en virgule fixe, in: Actes du GRETSI, Troyes, France, Sep. 2007, p. 577–580.

[43]

T. Saïdi, S. Roy, O. Sentieys.
A testbed for evaluation of MIMO WCDMA architectures, in: Signals, Systems and Electronics, 2007. ISSSE'07. International Symposium on, Montréal, Canada, July 2007.

[44]

R. Santoro, S. Roy, O. Sentieys.
Search for Optimal Five-Neighbor FPGA-Based Cellular Automata Random Number Generators, in: International Symposium on Signals, Systems and Electronics (ISSSE), Montréal, Canada, August 2007, p. 343–346.

[45]

O. Sentieys, O. Berder, P. Quemerais, M. Cartron.
Wake-up Interval Optimization fo Sensor Networks with Rendez-vous Schemes, in: Workshop on Design and Architectures for Signal and Image Processing (DASIP'07), Grenoble, France, November 2007.

[46]

C. Wolinski, K. Kuchcinski.
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware, in: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, USA, June 2007, p. 175–181.

[47]

C. Wolinski, K. Kuchcinski.
Identification of Application Specific Instructions Based on Subgraph Isomorphism Constraints, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Montreal, Canada, July 2007, p. 328–333.

Miscellaneous

[48]

A. Floc'h.
Compilation pour architectures reconfigurables, Masters thesis, University of Rennes, June 2007.

[49]

A. Pasha.
Power Optimization of Channel Coder and Decoder Adapted for Wireless Sensor Networks, Masters thesis, University of Nice-Sophia Antipolis, June 2007.

References in notes

[50]

AIS.
Application Notes and Interpretation of the Scheme (AIS), 1999.

[51]

L. Benini, G. D. Micheli.
Networks on Chips: a New SoC Paradigm, in: IEEE Computer, January 2002, vol. 35, n^o 1, p. 70–78.

[52]

D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.

[53]

W. Dally, B. Towles.
Route Packets, Not Wires: on-chip Interconnection Networks, in: Proceedings of the 38th Design Automation Conference, June 2001.

[54]

J. J. da Silva, J. Shamberger, J. Ammer, C. Guo, S. Li, R. Shah, T. Tuan, M. Sheets, J. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright.
Design Methodology for PicoRadio Networks, in: Design, Automation and Test in Europe Conference, IEEE/ACM, 2001.

[55]

A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, Ph. D. Thesis, MIT, 1996.

[56]

FIPS.
Security Requirements for Cryptographic Modules, FIPS PUB 140-2, 1999
http://csrc.nist.gov/publications/fips/fips140-2/fips1402.pdf.

[57]

R. Gallager.
Low-density parity-check codes, in: IRE Trans. Inform. Theory, Jan. 1962, vol. 8, p. 21-28.

[58]

A. Goldsmith, S. Wicker.
Design Challenges for Energy-Constrained Ad Hoc Wireless Networks, in: IEEE Wireless Communications, August 2002, vol. 9, n^o 4, p. 8–27.

[59]

S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, April 2000.

[60]

T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, October 1996.

[61]

S. Guyetant, M. Giraud, L. L'Hours, S. Derrien, S. Rubini, D. Lavenier, F. Raimbault.
Cluster of Reconfigurable Nodes for Scanning Large Genomic Banks, in: Parallel Computing, 2005, vol. 31, n^o 1, p. 73–96.

[62]

R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.

[63]

S. Hauck, T. Fry, M. Hosler, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.

[64]

J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, June 1997.

[65]

H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, June 2001.

[66]

K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, December 2000, vol. 19, n^o 12.

[67]

K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, September 2000, vol. 47, p. 840-848.

[68]

L. L'Hours.
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications, in: Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, S. Vassiliadis, N. Dimopoulos, S. Rajopadhye (editors), IEEE Computer Society, July 2005, p. 127–133.

[69]

R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.

[70]

G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.

[71]

G. Marsaglia.
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[72]

S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, June 1999.

[73]

J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), June 2000.

[74]

A. Rukhin, J. Soto, J. Nechvatal, M. Smid, D. Banks.
A Statistical Test Suite for Random and Pseudorandom Number Generators for Statistical Applications, in: NIST Special Publication in Computer Security, 2001, p. 800-22.

[75]

C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.

[76]

A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, November 2001.

[77]

R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Technical report, HP Laboratories Palo Alto, October 2001, n^o HPL-2001-249.

[78]

M. Srivastava.
Power-aware Communication Systems, in: Power-aware Design Methodologies, M. Pedram, J. Rabaey (editors), Kluwer Academic Publishers, 2002, chap. 11, p. 297–334.

[79]

M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.