Section: New Results
Energy-aware control for systems on-chip
The NeCS team is involved in the ARAVIS project (see 7.1 ) : the high level of integration in future chips will lead to heterogeneity in the performance of the various integrated components. It appears that introducing control loops at different levels of these chips will be necessary to be compliant with heterogeneous circuits.
Adaptive Control of the Boost DC-AC Converter
The control of boost DC-AC converters is usually accomplished tracking a reference (sinusoidal) signal. The use of this external signal makes the closed-loop control system to be non-autonomous and thus, making its analysis involved. Here we follow a different approach consisting in design a control law in order to stabilise a limit cycle corresponding to the desired oscillatory behaviour. In that way, no external signals are needed. In [Oops!] we have proposed an adaptive control law for the nonlinear boost inverter in order to cope with unknown resistive load. This adaptive control is accomplished by using a state observer to one side of the inverter and by measuring the state variables. The stability properties are derived by resting to via singular perturbation analysis.
Energy aware computing power control
Achieving a good compromise between computing power and energy consumption is one of the challenge in embedded architecture of the future. This management is especially difficult for 45nm or 32nm known to be at the limit of the scalability. Automatic control loops have therefore to be designed in order to make the performance fit the requirement in order to minimise the energy loss in a context of highly unknown performance of the chip. The main objective is to control the computing power and the consumption using the voltage and frequency automatically according to the requirements of the OS. For this, appropriate sensors must be implemented on the chip and a high-performance repartition between hardware and software implementation must be made.
An application software deployment based on a static and worst case point of view is no longer effective for such heterogeneous chips and more flexible designs must be used. It appears that closed-loop control can be integrated at several hardware and software levels of the chips to provide both adaptivity to the operation conditions and robustness w.r.t. variability.
On top of the nodes power control and computing speed control layers, the outer application layer will include a closed-loop controller of the application quality of service (QoS) under constraints of computing and energy resources availability. This loop uses the scheduling parameters provided by the operating system to regulate the application's QoS. In the context of Aravis the computing speed of each integrated node is assumed to be controllable and is also a possible control actuator used by the application level. A first step will be devising a formal definition of the required control performance and stating cost functions to formally associate the QoS with the usable scheduling parameters.